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Visitor avigailr
Visitor
3,697 Views
Registered: ‎01-18-2018

UVM testbench

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Hi,

 

Trying to run a UVM testbench using vivado and VCS simulator.

"UVM_HOME" is set to "/usr/synopsys/vcs-mx/M-2017.03-SP1/etc/uvm-1.2/".

After export_simulation command, we use the following:

 

 

vlogan_opts="-full64 -kdb -lca -timescale=1ns/1ps +incdir+/usr/synopsys/vcs-mx/M-2017.03-SP1//etc/uvm-1.2//src /usr/synopsys/vcs-mx/M-2017.03-SP1//etc/uvm-1.2//src/uvm.sv /usr/synopsys/vcs-mx/M-2017.03-SP1//etc/uvm-1.2//src/dpi/uvm_dpi.cc -ntb_opts uvm"
vhdlan_opts="-full64"
vcs_elab_opts="-full64 -t ps -licqueue -l elaborate.log -debug_access+all"
vcs_sim_opts="-ucli -licqueue -l simulate.log +ntb_random_seed_automatic "

 

We get the following error at run time:

 

Error-[DPI-DIFNF] DPI import function not found
/usr/synopsys/vcs-mx/M-2017.03-SP1//etc/uvm-1.2//src/base/uvm_resource.svh, 386
  The definition of DPI import function/task 'uvm_glob_to_re' does not exist.
  Please check the stated DPI import function/task is defined, and its
  definition is either passed in a source file at compile-time, or provided in
  a shared library specified using the LRM Annex-J options at run-time.

And get the following error:

 

When we duplicate the "+incdir..." both to the vlogan and the elaborate phase, we get a compilation error:

 

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "/usr/synopsys/vcs-mx/M-2017.03-SP1//etc/uvm/uvm_pkg.sv", 31: token is ';'
  package uvm_pkg;

 

When using the following command for using VCS (without vivado), then the testbech runs OK.

 

 vcs  -full64 '-timescale=1ns/1ns' '-sverilog' +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc   design.sv testbench.sv  '+UVM_TESTNAME=mem_wr_rd_test'    -R

Is it possible to have a UVM env and run it using vivado and VCS simulator? What are the necessary compilation directives?

 

Thanks!

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Visitor avigailr
Visitor
4,544 Views
Registered: ‎01-18-2018

Re: UVM testbench

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Hi all,

Thanks very much for the links and tips, when we substitute the compiler directives in the output script of "export_simulation" with the following directives, then UVM is loaded (also allows to use Verdi as GUI):

 

 

vlogan_opts="-full64 -kdb -lca -timescale=1ns/1ps +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc +incdir+$UVM_HOME/vcs $UVM_HOME/vcs/uvm_custom_install_vcs_recorder.sv +incdir+$UVM_HOME/verdi $UVM_HOME/verdi/uvm_custom_install_verdi_recorder.sv -CFLAGS -DVCS -ntb_opts uvm"
vhdlan_opts="-full64"
vcs_elab_opts="-full64 -t ps -licqueue -l elaborate.log -debug_access+all -ntb_opts uvm"
vcs_sim_opts="-ucli -licqueue -l simulate.log +UVM_TESTNAME=test_a +ntb_random_seed_automatic"

 

Hopefully it may help someone else..

 

Is there any way passing these directives as arguments to the "export_simulation" command?

Or maybe compiling the UVM included dirs to a lib, and then load it to the run as "uvm_lib" instead of compiling them for each run?

 

Thanks again :)

 

 

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Moderator
Moderator
3,680 Views
Registered: ‎04-24-2013

Re: UVM testbench

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Hi @avigailr,

 

I found the following example of running a UVM testbench with Vivado and VCS Simulator which may be useful

 

https://forums.xilinx.com/t5/Simulation-and-Verification/System-verilog-UVM-simulation-for-Xilinx-EMAC/td-p/274612

 

Best Regards
Aidan

 

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Scholar dpaul24
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Registered: ‎08-07-2014

Re: UVM testbench

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@avigailr,

 

It is very much possible that UVM runs without any problems in VCS but fails with Vivado.

Because UVM might not yet be supported on Vivado simulator. Let a Xilinx personnel confirm this.

 

btw - Have you tried out the Batch/Script mode in Vivado Simulator, pp 122 on https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug900-vivado-logic-simulation.pdf

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Visitor avigailr
Visitor
4,545 Views
Registered: ‎01-18-2018

Re: UVM testbench

Jump to solution

 

Hi all,

Thanks very much for the links and tips, when we substitute the compiler directives in the output script of "export_simulation" with the following directives, then UVM is loaded (also allows to use Verdi as GUI):

 

 

vlogan_opts="-full64 -kdb -lca -timescale=1ns/1ps +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc +incdir+$UVM_HOME/vcs $UVM_HOME/vcs/uvm_custom_install_vcs_recorder.sv +incdir+$UVM_HOME/verdi $UVM_HOME/verdi/uvm_custom_install_verdi_recorder.sv -CFLAGS -DVCS -ntb_opts uvm"
vhdlan_opts="-full64"
vcs_elab_opts="-full64 -t ps -licqueue -l elaborate.log -debug_access+all -ntb_opts uvm"
vcs_sim_opts="-ucli -licqueue -l simulate.log +UVM_TESTNAME=test_a +ntb_random_seed_automatic"

 

Hopefully it may help someone else..

 

Is there any way passing these directives as arguments to the "export_simulation" command?

Or maybe compiling the UVM included dirs to a lib, and then load it to the run as "uvm_lib" instead of compiling them for each run?

 

Thanks again :)

 

 

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