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Visitor pixart_pg
Visitor
8,089 Views
Registered: ‎09-29-2015

Unable to generate SDF files in Plan Ahead 14.7

Design Tool : Plan Ahead 14.7

Simulator : NC SIM

 

We're trying to generate SDF(.sdf) and Verilog Simulation Netlist File (.v).

 

TCL Command : write_verilog /net/project_path/GL_TIMESIM.v -mode timesim -sdf_anno true

 

Results:

Tcl Console: 

Warning : [Designutils 20-195] Net din has conflicting value (<N6> vs. <N12>) on different bits for attribute USER_ALIAS

Warning : [Designutils 20-195] Net din has conflicting value (<N108> vs. <N114>) on different bits for attribute USER_ALIAS

Warning : [Designutils 20-195] Net din has conflicting value (<N103> vs. <N107>) on different bits for attribute USER_ALIAS

write_verilog : Time (s) : cpu = 00:00:06 ; elapsed = 00:00:06, Memory (MB) : peak = 1285.062; gain = 0.125

/net/project_path/GL_TIMESIM.v 

 

Trying to search for sdf file, but can't find in project path. I expect NCSIM support the verilog simulation netlist and sdf as we did it using ISE 10.1i (previous project).

 

 

 

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9 Replies
Xilinx Employee
Xilinx Employee
8,079 Views
Registered: ‎04-16-2012

Re: Unable to generate SDF files in Plan Ahead 14.7

Hello @pixart_pg

 

Can you check whether the SDF file has generated in the following locations:

 

1. <project_location>/project.sim/sim_1/

2. present working directory i.e., pwd

 

As there are only warnings generated, I expect the tool to generate sdf file.

 

Thanks,

Vinay

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Moderator
Moderator
8,072 Views
Registered: ‎04-17-2011

Re: Unable to generate SDF files in Plan Ahead 14.7

Did you see in the log a message as " SDF Annotation successful" ? Are you running the command outside PA or from the GUI itself?
Regards,
Debraj
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Xilinx Employee
Xilinx Employee
8,069 Views
Registered: ‎08-01-2008

Re: Unable to generate SDF files in Plan Ahead 14.7

check this related ARS
http://www.xilinx.com/support/answers/53242.html
Thanks and Regards
Balkrishan
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Visitor pixart_pg
Visitor
8,064 Views
Registered: ‎09-29-2015

Re: Unable to generate SDF files in Plan Ahead 14.7

Yes. It's safely to ignore the warning but why there's no SDF file generated. From the help description, the SDF fil should be generate if you specify the -sdf_annotated true.
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Visitor pixart_pg
Visitor
8,054 Views
Registered: ‎09-29-2015

Re: Unable to generate SDF files in Plan Ahead 14.7

No. I'm running this command in PA GUI's tcl console.

 

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Visitor pixart_pg
Visitor
8,041 Views
Registered: ‎09-29-2015

Re: Unable to generate SDF files in Plan Ahead 14.7

Anyone can help for this issue?

 

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Visitor pixart_pg
Visitor
8,025 Views
Registered: ‎09-29-2015

Re: Unable to generate SDF files in Plan Ahead 14.7

Can anyone confirm that the SDF file generation is working in Plan Ahead 14.7?

 

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Visitor pixart_pg
Visitor
8,012 Views
Registered: ‎09-29-2015

Re: Unable to generate SDF files in Plan Ahead 14.7

Anyone can help on this issue?

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Xilinx Employee
Xilinx Employee
8,009 Views
Registered: ‎04-16-2012

Re: Unable to generate SDF files in Plan Ahead 14.7

Hello @pixart_pg

 

I followed below steps in planAhead to generate the sdf file:

 

  1. Open project and ran implementation
  2. Open the implemented design
  3. Ran the tcl command: write_verilog /path/to/file/timesim.v -mode timing -sdf_anno true -sdf_file bft_tb_time_impl.sdf
  4. Ran timing simulation and I observed bft_tb_time_impl.sdf file in project_name.sim/sim_1/impl/timing folder.

Thanks,

Vinay

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