09-29-2015 07:45 PM
Design Tool : Plan Ahead 14.7
Simulator : NC SIM
We're trying to generate SDF(.sdf) and Verilog Simulation Netlist File (.v).
TCL Command : write_verilog /net/project_path/GL_TIMESIM.v -mode timesim -sdf_anno true
Warning : [Designutils 20-195] Net din has conflicting value (<N6> vs. <N12>) on different bits for attribute USER_ALIAS
Warning : [Designutils 20-195] Net din has conflicting value (<N108> vs. <N114>) on different bits for attribute USER_ALIAS
Warning : [Designutils 20-195] Net din has conflicting value (<N103> vs. <N107>) on different bits for attribute USER_ALIAS
write_verilog : Time (s) : cpu = 00:00:06 ; elapsed = 00:00:06, Memory (MB) : peak = 1285.062; gain = 0.125
Trying to search for sdf file, but can't find in project path. I expect NCSIM support the verilog simulation netlist and sdf as we did it using ISE 10.1i (previous project).
09-29-2015 08:11 PM
Can you check whether the SDF file has generated in the following locations:
2. present working directory i.e., pwd
As there are only warnings generated, I expect the tool to generate sdf file.
09-29-2015 08:40 PM
09-29-2015 08:48 PM
09-29-2015 10:12 PM
10-06-2015 08:58 PM
I followed below steps in planAhead to generate the sdf file: