05-06-2019 05:02 AM
I am trying to do a project that uses the UltraScale PCIe DMA Xilinx IP. I have configured the IP as follows:
The problem is, when I try to simulate the design, I get the following:
ERROR: [VRFC 10-2063] Module <xdma_v4_1_1_dma_bram_wrap> not found while processing module instance <MASTER_WRITE_FIFO> [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xdma_v4_1/hdl/xdma_v4_1_vl_rfs.sv:39649] ERROR: [VRFC 10-2063] Module <xdma_v4_1_1_dma_bram_wrap> not found while processing module instance <MASTER_READ_BRAM> [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xdma_v4_1/hdl/xdma_v4_1_vl_rfs.sv:39666] ERROR: [VRFC 10-2063] Module <xdma_0_pcie3_ip> not found while processing module instance <pcie3_ip_i> [/home/viniciusglinden/VivadoProjects/PCIe-BERT/PCIe-BERT.srcs/sources_1/ip/xdma_0/xdma_v4_1/hdl/verilog/xdma_0_core_top.sv:4720]
I have tried deleting the IP, redoing it, resetting the output products, generating output producs as global and also did a simpler project to simulate the IP with the same configuration successfuly. So I have no idea why this is happening.
My configuration is: CentOS with Vivado 2018.2 installed. The board that I am using is the KCU105.
05-08-2019 02:44 PM
I took the simulation that was working, made a copy and replacedd all the files with the original one, except the IP. It works.
This is certainly an issue with Vivado 2018.2, isn't it?
05-09-2019 07:14 AM
Hi @vgl94 ,
Can you please try using Vivado 2018.3 and check if you are facing the issue. If the issue is still seen then can you please share the archived project or the test case to check this issue at our end.
05-10-2019 11:35 AM
I have installed Vivado 2018.3 as you requested and opened the project. But now I got different silly errors, which are not the same as the last.
I don't know why this is happening, but I thank you for your patience. This is no longer a concern of mine, since I got it working with a work-around.