cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
541 Views
Registered: ‎05-18-2018

Undefined FIFO output signal

Can someone explain why the wr_rst_busy is undefined after reset for some clock cycles?

Cattura.PNG
0 Kudos
9 Replies
Highlighted
Moderator
Moderator
535 Views
Registered: ‎08-08-2017

Re: Undefined FIFO output signal

Hi m@rx 

What simulation is this ?  Behavioral , Post synthesis/post implementation functional or timing?

Are you using FIFO generator or XPM based implemetation?   Please share the .xci or XPM FIFO macro instatiation

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
473 Views
Registered: ‎05-18-2018

Re: Undefined FIFO output signal

Hi pthakare,

This is a behavioral simulation. I used the FIFO generator.

How can I share .xci files? It can not be attached. And obviously it is not allowed to share external links?

Thank you

0 Kudos
Highlighted
Moderator
Moderator
469 Views
Registered: ‎08-08-2017

Re: Undefined FIFO output signal

Hi m@rx 

Change the extention (say .xca) and try to attach ?

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
466 Views
Registered: ‎05-18-2018

Re: Undefined FIFO output signal

I tried .txt which did not work.

0 Kudos
Highlighted
Moderator
Moderator
458 Views
Registered: ‎08-08-2017

Re: Undefined FIFO output signal

Hi m@rx 

I sent you EZMOVE FTP link on your ID .

Please attach .xci there.

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
450 Views
Registered: ‎05-18-2018

Re: Undefined FIFO output signal

Hi pthakare,

I submitted the .xci file. Could you please remove my email from this post. Thank you.

0 Kudos
Highlighted
Adventurer
Adventurer
436 Views
Registered: ‎04-04-2018

Re: Undefined FIFO output signal

As a datapoint, I ran a test in Vivado 2019.1 with a FIFO I had already generated. I opened the example design, ran behavioral sim, and see the same unknown state in the wr_rst_busy signal right out of the verilog model.
Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com
0 Kudos
Highlighted
Observer
Observer
420 Views
Registered: ‎05-18-2018

Re: Undefined FIFO output signal

@markgrafbut this must not be the case. since it is a control signal it needs to be defined. Seems like a bug.

0 Kudos
Highlighted
Adventurer
Adventurer
404 Views
Registered: ‎04-04-2018

Re: Undefined FIFO output signal

I agree, seems like a bug. I would submit a service request with Xilinx as the issues is in the model.

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com
0 Kudos