09-04-2019 11:02 AM
Can someone explain why the wr_rst_busy is undefined after reset for some clock cycles?
09-04-2019 11:06 AM - edited 09-04-2019 11:08 AM
Hi m@rx
What simulation is this ? Behavioral , Post synthesis/post implementation functional or timing?
Are you using FIFO generator or XPM based implemetation? Please share the .xci or XPM FIFO macro instatiation
09-05-2019 04:44 AM
Hi pthakare,
This is a behavioral simulation. I used the FIFO generator.
How can I share .xci files? It can not be attached. And obviously it is not allowed to share external links?
Thank you
09-05-2019 04:47 AM
Hi m@rx
Change the extention (say .xca) and try to attach ?
09-05-2019 04:49 AM
09-05-2019 04:59 AM - edited 09-05-2019 09:43 PM
Hi m@rx
I sent you EZMOVE FTP link on your ID .
Please attach .xci there.
09-05-2019 05:22 AM
Hi pthakare,
I submitted the .xci file. Could you please remove my email from this post. Thank you.
09-05-2019 11:48 AM
09-05-2019 04:47 PM
@markgrafbut this must not be the case. since it is a control signal it needs to be defined. Seems like a bug.
09-05-2019 06:53 PM
I agree, seems like a bug. I would submit a service request with Xilinx as the issues is in the model.