Undefined FIFO output signal

[m@rx]

Can someone explain why the wr_rst_busy is undefined after reset for some clock cycles?

[pthakare]

Hi m@rx 

What simulation is this ?  Behavioral , Post synthesis/post implementation functional or timing?

Are you using FIFO generator or XPM based implemetation?   Please share the .xci or XPM FIFO macro instatiation

[m@rx]

Hi pthakare,

This is a behavioral simulation. I used the FIFO generator.

How can I share .xci files? It can not be attached. And obviously it is not allowed to share external links?

Thank you

[pthakare]

Hi m@rx 

Change the extention (say .xca) and try to attach ?

[m@rx]

I tried .txt which did not work.

[pthakare]

Hi m@rx 

I sent you EZMOVE FTP link on your ID .

Please attach .xci there.

[m@rx]

Hi pthakare,

I submitted the .xci file. Could you please remove my email from this post. Thank you.

[markgraf]

As a datapoint, I ran a test in Vivado 2019.1 with a FIFO I had already generated. I opened the example design, ran behavioral sim, and see the same unknown state in the wr_rst_busy signal right out of the verilog model.

[m@rx]

@markgrafbut this must not be the case. since it is a control signal it needs to be defined. Seems like a bug.

[markgraf]

I agree, seems like a bug. I would submit a service request with Xilinx as the issues is in the model.