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Observer
Observer
9,242 Views
Registered: ‎06-28-2015

Undifined values by Simuation in vivado.

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hi ,

 

I write  a testbensch for a created  IP block ( FIR filter ) .

 

i receive in all input and output signals an undifined value !  Please i need help .

 

the testbensch is written  in vhdl (see below ):

 

Unbenannt.jpg

 

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.08.2015 22:24:23
-- Design Name:
-- Module Name: testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity testbench is
--  Port ( );
end testbench;

architecture Behavioral of testbench is

component design_1 is
  port (
    S_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S_AXIS_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S_AXIS_tlast : in STD_LOGIC;
    S_AXIS_tvalid : in STD_LOGIC;
    S_AXIS_tready : out STD_LOGIC;
    M_AXIS_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXIS_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXIS_tlast : out STD_LOGIC;
    M_AXIS_tvalid : out STD_LOGIC;
    M_AXIS_tready : in STD_LOGIC;
    s_axis_aclk : in STD_LOGIC;
    s_axis_aresetn : in STD_LOGIC
  );
  end component design_1;
 
  ----------------------------------------------------------------------------------------
  -- Signal declaration
 
 signal  CLK : std_logic :='0';
 signal  M_AXIS_tdata : STD_LOGIC_VECTOR (31 downto 0):= (others => '0');
 signal  S_AXIS_tdata :  STD_LOGIC_VECTOR (31 downto 0):= (others => '0');
 signal  S_AXIS_tstrb :STD_LOGIC_VECTOR   (3 downto 0):= (others => '0');
 signal  S_AXIS_tlast : std_logic :='0';
 signal  S_AXIS_tvalid : std_logic :='0';
 signal  S_AXIS_tready : std_logic :='0';
 signal  M_AXIS_tstrb :  STD_LOGIC_VECTOR (3 downto 0):= (others => '0');
 signal  M_AXIS_tlast : std_logic :='0';
 signal  M_AXIS_tvalid : std_logic :='0';
 signal  M_AXIS_tready : std_logic :='0';
 signal  s_axis_aresetn : std_logic :='0';
 signal  m_axis_aresetn : std_logic :='0';
 
 constant Clk_period : time := 10 ns;

begin

U1 : design_1 port map (
  S_AXIS_tdata => S_AXIS_tdata,
   S_AXIS_tstrb => S_AXIS_tstrb,
   S_AXIS_tlast => S_AXIS_tlast,
   S_AXIS_tvalid => S_AXIS_tvalid,
   S_AXIS_tready => S_AXIS_tready,
   M_AXIS_tdata => M_AXIS_tdata,
   M_AXIS_tstrb => M_AXIS_tstrb,
   M_AXIS_tlast=> M_AXIS_tlast,
   M_AXIS_tvalid => M_AXIS_tvalid,
   M_AXIS_tready => M_AXIS_tready,
   s_axis_aclk => CLK,
  s_axis_aresetn => s_axis_aresetn
);
 -- Clock process definitions
  Clk_process :process
  begin
       Clk <= '0';
       wait for Clk_period/2;
       Clk <= '1';
       wait for Clk_period/2;
  end process;
 
 
     -- Stimulus process
  stim_proc: process
  begin       
     wait for Clk_period*2;
       Xin <=X"A1278943" ; wait for clk_period*1;
       Xin <=X"A1232306" ; wait for clk_period*1;
       Xin <=X"1245A123" ; wait for clk_period*1;

      
     wait;
  end process;

 

end Behavioral;

 

 

 

thanks

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Xilinx Employee
Xilinx Employee
17,049 Views
Registered: ‎10-24-2013

Hi,

 

From the sources window, select the correct topr file to get the things working fine.

 

Thanks,Vijay
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Professor
Professor
9,141 Views
Registered: ‎08-14-2007

It looks like you are starting the simulation with the "design_1" entity as the top level rather than your test bench.  This usually occurs when you select the wrong source when starting the simulator from the GUI.

-- Gabor
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Xilinx Employee
Xilinx Employee
17,050 Views
Registered: ‎10-24-2013

Hi,

 

From the sources window, select the correct topr file to get the things working fine.

 

Thanks,Vijay
--------------------------------------------------------------------------------------------
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Give kudos in case a post in case it guided to the solution.

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Observer
Observer
9,048 Views
Registered: ‎06-28-2015

thank you   but when i set select my testbensch as Top , i receive this error message :

 

Unbenannt.png

 

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Xilinx Employee
Xilinx Employee
9,040 Views
Registered: ‎05-07-2015

Hi,

This error sometimes might come due to  language construct usage related errors Please check your test bench thoroughly for things like incomplete/wrong port-mapping etc.

General advice:

It is advised to use "wait for Clk_period" only in Clock generation process.

IN the stim_proc:
Use  "WAIT UNTIL rising_edge(Clk)"  instead of "wait for Clk_period".

 This practice ensures anticipated simulation results.


Thanks
Bharath
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Professor
Professor
9,026 Views
Registered: ‎08-14-2007

Looking at the hierarchy showing in the image, I see an entity called "test" where I would have expected one called "testbench" to match the code in the first post.  If you have not changed the entity name of the testbench, this seems to say that you have some other (possibly historical) file attached to the project rather than the testbench you are trying to use.  Make sure that the testbench you posted is actually included in the project.  You can double-click on the entity "test" in the hierarchy pane to open it in a text editor and see what is in it.

 

Also in the image I see an error:

 

s_axis_aresetn is not declared

 

However it is clearly declared in the code from the first post.  This seems to confirm that some other source is being used in the actual project.

-- Gabor
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Observer
Observer
8,971 Views
Registered: ‎06-28-2015
thanks . it works now .
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