cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
11,350 Views
Registered: ‎11-23-2015

Unexepted EOF : missing `endif

Jump to solution

I am converting an ASIC design that has been verified in simulation, to a Vivado project.

On input the syntax checker is reporting 10 instances of:

 

[HDL 9-850] Unexpected EOF : missing `endif <filename.v>

 

We have checked all the files and every `ifdef / `ifndef / `elsif has a corresponding `endif  as already verified by the other simulator

 

Any suggestions on what to look for next?

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Visitor
Visitor
20,463 Views
Registered: ‎11-23-2015

We have resolved the issue.

 

The problem is NOT a dangling `ifdef, `endif or the like.  Rather it was a dangling "// synopsys  translate_off" which, of course, our ASIC simulator ignored.  As there was no coresponding "// synopsys  translate_on" the whole code base was messed up.  That it only affected 10 files out of about 40 or so is remarkable!

Thank you evryone for your help.  It did eventually lead to a resolution

 

 

 

 

View solution in original post

8 Replies
Highlighted
Scholar
Scholar
11,346 Views
Registered: ‎02-27-2008

Check for a carriage return, line feed at the end,

 

I have seen some editors/tools reject .v files without a blank line at the end.

 

I usually see this when I use someone elses files for ptotoyping an ASIC in an FPGA (they used completely different tools).

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Highlighted
Visitor
Visitor
11,334 Views
Registered: ‎11-23-2015

Hmmm.   Checked the 10 files that Vivado complains about and added a few extra lines on the end

 

Same result!

 

Checked all the files in the design and did the same to them all

 

Same result!

 

Same 10 files everytime that have the error.  Some of them have no `ifdef/`endif statements at all

 

Any more ideas

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
11,329 Views
Registered: ‎08-02-2011
I usually see this when I forget the 'endmodule' at the end.
www.xilinx.com
0 Kudos
Highlighted
Visitor
Visitor
11,322 Views
Registered: ‎11-23-2015

Nope I have all of them!

Besides it wouldn't simulate in the ASIC environment without the correct number of 'endmodules'

0 Kudos
Highlighted
Moderator
Moderator
11,303 Views
Registered: ‎07-01-2015

Hi @rtt42,

 

Can you please attach the code here in which you are getting warning?

Is "begin" is ended with "end"?

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Explorer
Explorer
11,286 Views
Registered: ‎04-28-2015

Hi @rtt42

 

Can you post any one of these files (or a test snippet) which can reproduce this issue?

 

Regards,

Tushar

 

0 Kudos
Highlighted
Moderator
Moderator
11,280 Views
Registered: ‎06-24-2015
Hi @rtt42 ,

Can you try by inserting a semicolon at the end of files?

Thanks,
Nupur
Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).
0 Kudos
Highlighted
Visitor
Visitor
20,464 Views
Registered: ‎11-23-2015

We have resolved the issue.

 

The problem is NOT a dangling `ifdef, `endif or the like.  Rather it was a dangling "// synopsys  translate_off" which, of course, our ASIC simulator ignored.  As there was no coresponding "// synopsys  translate_on" the whole code base was messed up.  That it only affected 10 files out of about 40 or so is remarkable!

Thank you evryone for your help.  It did eventually lead to a resolution

 

 

 

 

View solution in original post