cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Newbie
Newbie
9,565 Views
Registered: ‎10-14-2015

Unisim conflict - Verilog vs VHDL

Hi,

 

I am using ModelSim PE 10.4c and Mentor HDL Designer flow to compile/start the simulation. The project I am dealing with is the PCIe v31 generated with Xilinx Vivado 2015.2 (EP and RP).

 

When starting the simulation, HDL Designer takes as default the unisim VHDL library. One can add further libraries (e.g. -Lf unisims_ver) but not remove the unisim VHDL library. This produces some conflicts when loading and/or running the simulation.

 

  1. Simulating with unisim only: fail to load
  2. Simulating with unisim and unisims_ver (with load first -Lf option): loading, failing at run
  3. Simulating with unisims_ver only: working (both loading and running)
  4. Simulating with unisims_ver and unisim (where unisims_ver the 1st in the vsim command line is) works!

But since 3 and 4 are not options (due to the restricted HDL Designer flow) I need another solution.

 

My understanding of the problem is that unisim VHDL is a bad translation of unisims Verilog. It has to do with how boolean generics/parameters are interpreted.

 

One of the errors I am getting in the file /src/unisims/primitive/MMCME2_ADV.vhd Line: 139

 

Fatal: (vsim-3729) Value ?(1095521093) of generic "CLKFBOUT_USE_FINE_PS" is out of range FALSE (0) to TRUE (1).

 

 

When checking how the CLKFBOUT_USE_FINE_PS generic is defined I found following:

 

In VHDL unisim source as boolean:   

CLKFBOUT_USE_FINE_PS : boolean  := FALSE;

In Verilog unisim source as string: 

parameter CLKFBOUT_USE_FINE_PS = "FALSE";

The module MMCME2_ADV is referenced in my design in a verilog source (a7_pcie_v3_1_pipe_clock.v).

 

MMCME2_ADV #
(
..... .CLKFBOUT_USE_FINE_PS ("FALSE"),

My understanding is that the design should be simulatable no matter what library (vhdl or verilog) is used. It is however not the case. Is this a known problem of Unisim? Does Xilinx offer any solution for it?

I would not want to patch the generated files (unisim or pcie), such changes get lost when re-generating or upgrading the tool version.

 


 

I have attached a test design that exemplifies the issues one gets when not loading the _ver libraries or mixing vhdl and _ver.

 

0 Kudos
11 Replies
Highlighted
Teacher
Teacher
9,498 Views
Registered: ‎03-31-2012

Re: Unisim conflict - Verilog vs VHDL

is it not possible to generate vhd version of the pcie ip? if you could get a a7_pcie_v3_1_pipe_clock.vhd, that might solve your problem. Set your project language to vhdl before you generate the pcie ip and see if it works.

BTW, what is the "restricted HDL Designer flow" which allows you to do option 2 but not 4 ?
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Highlighted
Moderator
Moderator
9,493 Views
Registered: ‎07-01-2015

Re: Unisim conflict - Verilog vs VHDL

Hi @onaben,

 

Please go through the following link. It speaks about the similar scenario.
http://www.xilinx.com/support/answers/47724.html

 

Hope it helps.

 

Thanks.
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Teacher
Teacher
9,487 Views
Registered: ‎03-31-2012

Re: Unisim conflict - Verilog vs VHDL

@arpansur: The reason why is unclear but the original poster specifically excludes the solution in the AR you mention. The AR suggests the option #4 and for @onaben, this would not work.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Highlighted
Newbie
Newbie
8,363 Views
Registered: ‎01-14-2016

Re: Unisim conflict - Verilog vs VHDL

Hi oaben

 

I have exactly the same problem using an MMCM in my design. In HDL Author, you can change the order of used Verilog libraries (so solution 4) by doing the following:

 

- go to "Project" tab

- right-click to "My Project"

- select "Edit Verilog Library Search Path..."

- write "unisims_ver unisim" and press Ok

 

In the end, it should look as in the attached screenshot.

 

Hope, this helps.

 

Regards

 

Michael

Screenshot.PNG
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,251 Views
Registered: ‎10-24-2013

Re: Unisim conflict - Verilog vs VHDL

Hi @onaben

Did that solved your issue? Please post the status.

 

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Highlighted
Observer
Observer
502 Views
Registered: ‎01-25-2012

Re: Unisim conflict - Verilog vs VHDL

I am getting the following QuestaSim Runtime Error.

# [ 0] : System Reset Is Asserted...
# Error: [Unisim MMCME2_ADV-104] CLKFBOUT_USE_FINE_PS attribute is set to . Legal values for this attribute are TRUE or FALSE. Instance: tb_nano_hsod_fpga_full.RP.rport.genblk2.gt_top_i.pipe_wrapper_i.pipe_clock_int.pipe_clock_i.mmcm_i
# ** Note: $finish : C:/Xilinx/Vivado/2017.4/data/verilog/src/unisims/MMCME2_ADV.v(1192)
# Time: 2 ps Iteration: 0 Instance: /tb_nano_hsod_fpga_full/RP/rport/genblk2/gt_top_i/pipe_wrapper_i/pipe_clock_int/pipe_clock_i/mmcm_i

I assume it it being caused by the same Unisim issue.  Does anyone have a soultion for this?

Thanks

The libraries I have listed in my project is 

Capture.PNG

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
481 Views
Registered: ‎07-16-2008

Re: Unisim conflict - Verilog vs VHDL

This should be caused by parameter value type mismatch between VHDL and Verilog unisim libraries.

Specifically in this case, string vs. boolean:

MMCME2_ADV.v

parameter CLKFBOUT_USE_FINE_PS = "FALSE",

MMCME2_ADV.vhd

CLKFBOUT_USE_FINE_PS : boolean := FALSE;

There's an AR that addresses the same topic:

https://www.xilinx.com/support/answers/47724.html

 

In your case, it looks the MMCME2_ADV is instantiated in VHDL entity but unisims_ver is searched first. You may want to adjust the -L order to load unisim prior to unisims_ver.

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
454 Views
Registered: ‎01-25-2012

Re: Unisim conflict - Verilog vs VHDL

I have tried it both ways.

vsim -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/unimacro_ver -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/unisim -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/unimacro -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/secureip -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/unisims_ver work.tb_nano_hsod_fpga_full +TESTNAME=hsod_reg_test -voptargs=+acc

Gives me this error:before the simulation loads.

# ** Fatal: (vsim-3729) Value ?(1095521093) of generic "CLKOUT0_USE_FINE_PS" is out of range FALSE (0) to TRUE (1).
# Time: 0 ps Iteration: 0 Instance: /tb_nano_hsod_fpga_full/RP/rport/genblk2/gt_top_i/pipe_wrapper_i/pipe_clock_int/pipe_clock_i/mmcm_i File: C:/Xilinx/Vivado/2017.4/data/vhdl/src/unisims/primitive/MMCME2_ADV.vhd Line: 151
# FATAL ERROR while loading design
# Error loading design

When I put unisims_ver before unisim, 

vsim -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/unimacro_ver -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/unimacro -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/secureip -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/unisims_ver -L C:/questasim64_10.6b_lib/lib_vivado_2017.4.1/unisim work.tb_nano_hsod_fpga_full +TESTNAME=hsod_reg_test -voptargs=+acc

The design loads with No error, However when I run -all

I get this:

run -all
# [ 0] : System Reset Is Asserted...
# Error: [Unisim MMCME2_ADV-104] CLKFBOUT_USE_FINE_PS attribute is set to . Legal values for this attribute are TRUE or FALSE. Instance: tb_nano_hsod_fpga_full.RP.rport.genblk2.gt_top_i.pipe_wrapper_i.pipe_clock_int.pipe_clock_i.mmcm_i
# ** Note: $finish : C:/Xilinx/Vivado/2017.4/data/verilog/src/unisims/MMCME2_ADV.v(1192)
# Time: 2 ps Iteration: 0 Instance: /tb_nano_hsod_fpga_full/RP/rport/genblk2/gt_top_i/pipe_wrapper_i/pipe_clock_int/pipe_clock_i/mmcm_i

Any Ideas?

Thanks

-mike

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
421 Views
Registered: ‎07-16-2008

Re: Unisim conflict - Verilog vs VHDL

The error Error: [Unisim MMCME2_ADV-104] is defined in MMCME2_ADV.v and should be triggered when the CLKFBOUT_USE_FINE_PS value is incorrect.

How is MMCME2_ADV called in your HDL file? Is it Verilog or VHDL or both?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
397 Views
Registered: ‎01-25-2012

Re: Unisim conflict - Verilog vs VHDL

It looks like both the VHDL and the verilog files are being used.  If I put the Verilog Lib first I get an error in the VHDL file.  It I put the Verilog lib first I get an error in the VHDL file.  Refer to my previous post.

All thes files are called from xilinx generated files.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
382 Views
Registered: ‎07-16-2008

Re: Unisim conflict - Verilog vs VHDL

If both are called, simply adjusting the loading order doesn't resolve the conflict.

I cannot think of a easy way to accomplish this. Maybe you can use Verilog and VHDL configuration files to bind the specific MMCME2_ADV instances to the desired library.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos