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Newbie onaben
Newbie
9,009 Views
Registered: ‎10-14-2015

Unisim conflict - Verilog vs VHDL

Hi,

 

I am using ModelSim PE 10.4c and Mentor HDL Designer flow to compile/start the simulation. The project I am dealing with is the PCIe v31 generated with Xilinx Vivado 2015.2 (EP and RP).

 

When starting the simulation, HDL Designer takes as default the unisim VHDL library. One can add further libraries (e.g. -Lf unisims_ver) but not remove the unisim VHDL library. This produces some conflicts when loading and/or running the simulation.

 

  1. Simulating with unisim only: fail to load
  2. Simulating with unisim and unisims_ver (with load first -Lf option): loading, failing at run
  3. Simulating with unisims_ver only: working (both loading and running)
  4. Simulating with unisims_ver and unisim (where unisims_ver the 1st in the vsim command line is) works!

But since 3 and 4 are not options (due to the restricted HDL Designer flow) I need another solution.

 

My understanding of the problem is that unisim VHDL is a bad translation of unisims Verilog. It has to do with how boolean generics/parameters are interpreted.

 

One of the errors I am getting in the file /src/unisims/primitive/MMCME2_ADV.vhd Line: 139

 

Fatal: (vsim-3729) Value ?(1095521093) of generic "CLKFBOUT_USE_FINE_PS" is out of range FALSE (0) to TRUE (1).

 

 

When checking how the CLKFBOUT_USE_FINE_PS generic is defined I found following:

 

In VHDL unisim source as boolean:   

CLKFBOUT_USE_FINE_PS : boolean  := FALSE;

In Verilog unisim source as string: 

parameter CLKFBOUT_USE_FINE_PS = "FALSE";

The module MMCME2_ADV is referenced in my design in a verilog source (a7_pcie_v3_1_pipe_clock.v).

 

MMCME2_ADV #
(
..... .CLKFBOUT_USE_FINE_PS ("FALSE"),

My understanding is that the design should be simulatable no matter what library (vhdl or verilog) is used. It is however not the case. Is this a known problem of Unisim? Does Xilinx offer any solution for it?

I would not want to patch the generated files (unisim or pcie), such changes get lost when re-generating or upgrading the tool version.

 


 

I have attached a test design that exemplifies the issues one gets when not loading the _ver libraries or mixing vhdl and _ver.

 

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5 Replies
Teacher muzaffer
Teacher
8,942 Views
Registered: ‎03-31-2012

Re: Unisim conflict - Verilog vs VHDL

is it not possible to generate vhd version of the pcie ip? if you could get a a7_pcie_v3_1_pipe_clock.vhd, that might solve your problem. Set your project language to vhdl before you generate the pcie ip and see if it works.

BTW, what is the "restricted HDL Designer flow" which allows you to do option 2 but not 4 ?
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Moderator
Moderator
8,937 Views
Registered: ‎07-01-2015

Re: Unisim conflict - Verilog vs VHDL

Hi @onaben,

 

Please go through the following link. It speaks about the similar scenario.
http://www.xilinx.com/support/answers/47724.html

 

Hope it helps.

 

Thanks.
Arpan

Thanks,
Arpan
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Teacher muzaffer
Teacher
8,931 Views
Registered: ‎03-31-2012

Re: Unisim conflict - Verilog vs VHDL

@arpansur: The reason why is unclear but the original poster specifically excludes the solution in the AR you mention. The AR suggests the option #4 and for @onaben, this would not work.
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Newbie 860217
Newbie
7,807 Views
Registered: ‎01-14-2016

Re: Unisim conflict - Verilog vs VHDL

Hi oaben

 

I have exactly the same problem using an MMCM in my design. In HDL Author, you can change the order of used Verilog libraries (so solution 4) by doing the following:

 

- go to "Project" tab

- right-click to "My Project"

- select "Edit Verilog Library Search Path..."

- write "unisims_ver unisim" and press Ok

 

In the end, it should look as in the attached screenshot.

 

Hope, this helps.

 

Regards

 

Michael

Screenshot.PNG
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Xilinx Employee
Xilinx Employee
7,695 Views
Registered: ‎10-24-2013

Re: Unisim conflict - Verilog vs VHDL

Hi @onaben

Did that solved your issue? Please post the status.

 

Thanks,Vijay
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