10-14-2015 02:39 AM
I am using ModelSim PE 10.4c and Mentor HDL Designer flow to compile/start the simulation. The project I am dealing with is the PCIe v31 generated with Xilinx Vivado 2015.2 (EP and RP).
When starting the simulation, HDL Designer takes as default the unisim VHDL library. One can add further libraries (e.g. -Lf unisims_ver) but not remove the unisim VHDL library. This produces some conflicts when loading and/or running the simulation.
But since 3 and 4 are not options (due to the restricted HDL Designer flow) I need another solution.
My understanding of the problem is that unisim VHDL is a bad translation of unisims Verilog. It has to do with how boolean generics/parameters are interpreted.
One of the errors I am getting in the file /src/unisims/primitive/MMCME2_ADV.vhd Line: 139
Fatal: (vsim-3729) Value ?(1095521093) of generic "CLKFBOUT_USE_FINE_PS" is out of range FALSE (0) to TRUE (1).
When checking how the CLKFBOUT_USE_FINE_PS generic is defined I found following:
In VHDL unisim source as boolean:
CLKFBOUT_USE_FINE_PS : boolean := FALSE;
In Verilog unisim source as string:
parameter CLKFBOUT_USE_FINE_PS = "FALSE";
The module MMCME2_ADV is referenced in my design in a verilog source (a7_pcie_v3_1_pipe_clock.v).
MMCME2_ADV # (
..... .CLKFBOUT_USE_FINE_PS ("FALSE"),
My understanding is that the design should be simulatable no matter what library (vhdl or verilog) is used. It is however not the case. Is this a known problem of Unisim? Does Xilinx offer any solution for it?
I would not want to patch the generated files (unisim or pcie), such changes get lost when re-generating or upgrading the tool version.
I have attached a test design that exemplifies the issues one gets when not loading the _ver libraries or mixing vhdl and _ver.
11-14-2015 01:41 PM
11-14-2015 02:06 PM - edited 11-14-2015 02:07 PM
Please go through the following link. It speaks about the similar scenario.
Hope it helps.
11-14-2015 02:11 PM
01-14-2016 11:53 PM
I have exactly the same problem using an MMCM in my design. In HDL Author, you can change the order of used Verilog libraries (so solution 4) by doing the following:
- go to "Project" tab
- right-click to "My Project"
- select "Edit Verilog Library Search Path..."
- write "unisims_ver unisim" and press Ok
In the end, it should look as in the attached screenshot.
Hope, this helps.
01-21-2016 10:49 PM
Did that solved your issue? Please post the status.