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mhmontazeri61
Adventurer
Adventurer
2,800 Views
Registered: ‎08-26-2013

Unknown non-related timing simulation error

Hi,

During Simulation of a simple code with a process for handling bram addresses and data and a block ram, behavioral simulation was ok and post implementation timing simulation failed due to the following errors(in vivado 2017.1 tool):

 

Vivado Simulator 2017.1
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.1/bin/unwrapped/win64.o/xelab.exe -wto 05e12adfc7be44e8acfa1817272fc792 --debug typical --relax --mt 2 --maxdelay -L work -L simprims_ver -L secureip --snapshot TB_uut_time_impl -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 work.TB_uut work.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-380] binding entity \uut\ does not have generic gdest

[C:/Users/sim/sim.srcs/sim_1/imports/Desktop/TB_uut.vhd:43]
ERROR: [VRFC 10-380] binding entity \uut\ does not have generic gsrc

[C:/Users/sim/sim.srcs/sim_1/imports/Desktop/TB_uut.vhd:44]
ERROR: [VRFC 10-380] binding entity \uut\ does not have generic gupd

[C:/Users/sim/sim.srcs/sim_1/imports/Desktop/TB_uut.vhd:45]
ERROR: [VRFC 10-380] binding entity \uut\ does not have generic gups

[C:/Users/sim/sim.srcs/sim_1/imports/Desktop/TB_uut.vhd:46]
ERROR: [VRFC 10-380] binding entity \uut\ does not have generic gudd

[C:/Users/sim/sim.srcs/sim_1/imports/Desktop/TB_uut.vhd:47]
ERROR: [VRFC 10-380] binding entity \uut\ does not have generic guds

[C:/Users/sim/sim.srcs/sim_1/imports/Desktop/TB_uut.vhd:48]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

 

 

What is the problem?

Thanks

mhmontazeri61

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5 Replies
mhmontazeri61
Adventurer
Adventurer
2,764 Views
Registered: ‎08-26-2013

Hi,

All Xilinx tools have problem with testbenches include component instantiation with default component generic mapped in testbench. Very confusing...

 

Re

mhmontazeri61

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thakurr
Moderator
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Registered: ‎09-15-2016

Hi @mhmontazeri61

 

With the test case attached i am not able to reproduce the issue in 2017.1 as well as 2017.2. Post implementation timing simulation matches behavioral simulation and there are no such erros or warnings. Can you please check this if you are doing anything wrong or correct me if i am wrong?

Share your code to reproduce the issue.

 

Regards

Rohit

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Regards
Rohit
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bandi
Moderator
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2,710 Views
Registered: ‎09-15-2016

Hi @mhmontazeri61,

 

Can you please check these related posts and see if it helps:

https://forums.xilinx.com/t5/Simulation-and-Verification/binding-entity-does-not-have-generic/td-p/670537

https://forums.xilinx.com/t5/Simulation-and-Verification/Post-synthesis-simulation-error-VRFC-10-380-generics-issue/td-p/701966

 

 

If this doesnt help then can you please share your design to check at our end. Also, can you please let us know if you come across the same error while running post synthesis simulation ?

 

Regards,

Sravanthi B

 

 

Thanks & Regards,
Sravanthi B
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mhmontazeri61
Adventurer
Adventurer
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Registered: ‎08-26-2013

@thakurr,

your attached design was successful im my PC and my tool too. I can not understand the difference between these two designs. Please send me your private mail for sending codes if it's possible for you.

 

 

Re

mhmontazeri61

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thakurr
Moderator
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2,598 Views
Registered: ‎09-15-2016

Hi @mhmontazeri61

 

I have sent you the package through Ezmove link. Please upload your project there.

 

Regards

Rohit

Regards
Rohit
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