04-11-2012 02:36 AM
I want to test a digital card which has I/O and a JTAG port (some I/Os of the card are not connected to the JTAG chain).
To correctly stress de DUT card, I want to introduce a FPGA in the JTAG chain to provide stimuli to the DUT card's I/Os.
The FPGA pins would then be connected to the DUT I/Os and then JTAG signals could be applied to the card I/Os.
It seems quite simple, I'm just wondering if I've to load a design in the FPGA in order to correctly configure its pins (as floating maybe?) or if it will work with any pin state/any design?
Thank you for your comments,
04-11-2012 07:50 AM
The fpga device powers ON as all tristate (and if the option (pin) is selected, with all weak pullups, or no weak pullups).
JTAG is then able to take over any pin, and set it to any state you wish.
No design is required.
04-17-2012 02:52 AM