Used VHDL Option in EDKs "Simulation Library Compilation Wizard". But running Modelsim gives: ** Error: Failure to obtain a Verilog simulation license.

[aleicht]

Hello,

I followed the instructions outlined in the Xilinx document "EDK Concepts, Tools, and Techniques" , Appendix A "Simulation in Project Navigator with Modelsim".

In the "Simulation Library Compilation Wizard" I choose VHDL for "What HDLs does your simulator support?". 

But If I start the Simulate Behavioral Model process to run ModelSim it says: ** Error: Failure to obtain a Verilog simulation license.

Whats going wrong here ?

The Tools are:

Xilinx ISE Design Suite 11.4

Modelsim PE 6.6

[edv]

Hello,

If the EDK design includes Hard IP (MGTs, Hard PCIe, etc), you will run into this error for VHDL-only simulators as those libraries are provided in Encrypted verilog.  Refer to Xilinx AR 33118 for information on how to run simulations of this sort with VHDL only license.

If the EDK design does not include Hard IP, then it's possible some of the pcores in your design can only be described via a Verilog model.  If this is the issue, then ping the embedded community via the EDK discussion boards for more troubleshooting ideas.

Hope this helps.

Eddie