08-03-2017 01:53 PM
I'm trying to simulate a ZYNQ design targeting the 7020 and have been using the AXI BFM to emulate the PS component to great effect in behavioural simulations. Is it possible to utilize the AXI BFM during post-synthesis and post-implementation simulations? If so, what has to be done when using the Vivado simulator to make this work? Please let me know. Thanks!
08-04-2017 12:54 AM
No the AXI BFM has to be removed from the design for synthesis and implementation. Thus it cannot be used for post-synthesis/implementation simulations.
You can maybe try to add the AXI BFM only in the test bench.
FYI: From 2017.1, the AXI BFM has been replaced by the AXI VIP. This one does not have to be removed for synthesis but is replaced with wires.
08-06-2017 06:03 PM
firstname.lastname@example.org if you're using the BFM or Xilinx VIP only in the testbench, then nothing changes. Only the target of the AXI transactions change from RTL to gates. If you have your own testbench, and implement the PL separately it's quite easy to do this.
07-04-2019 06:33 AM - edited 07-04-2019 06:36 AM
let's say I developed a custom AXI IP, and I want to simulate it 'post synthesis' using the MPSoC VIP , I'd need to instantiate the VIP in my testbench, and hook one of the MPSoC VIP AXI interfaces to my 'DUT'. That DUT could be a complete block design containing AXI interconnect, my custom IP and some other stuff? For example :
So if I understand you correctly I would need to :
1) create a testbench file, and instantiate the MPSoC VIP in it
2) put the rest of the elements in a BD, add the necessary ports (S00_AXI, S01_AXI, clocks, resets, ...), and create a hdl wrapper of that BD
3) instantiate that wrapper in my testbench, and hook it up to the MSoC VIP instance
is that correct? If so, is there an example of this?