10-11-2018 05:26 AM
We run the simulation script present in "\pcie_7x_0_ex.ip_user_files\sim_scripts\pcie_axi4_lite_bram\ies" folder for pcie_axi4_lite_bram.bd block design.
We also generated the wrapper for pcie_axi4_lite_bram_wrapper.v which also compiled for simulation in Cadence IES.
We instantiated this wrapper in another top file pcie_7x_0_support.v, but while compiling this file we have the following error message:
pcie_axi4_lite_bram_wrapper pcie_axi4_lite_bram_wrapper_i (|ncelab: *E,CUVMUR (/mvfs/device/OH_FPGA/PROJ_OH_FPGA/src/pcie_7x_0_ex_V01/pcie_7x_0_ex/imports/pcie_7x_0_support.v,806|56): instance 'OH_FPGA_TOP_TB.EP@OH_FPGA_TOP<module>.pcie_7x_0_support_i@pcie_7x_0_support<module>.pcie_axi4_lite_bram_wrapper_i' of design unit 'pcie_axi4_lite_bram_wrapper' is unresolved in 'worklib.pcie_7x_0_support:v'.
Please help to solve this unresolved wrapper instance for simulation.
Can anyone tell how IP's present inside Block design is interconnected? are there additional files (like *.bd file) to be included in the simulation script for simulation to come up..
10-12-2018 02:45 AM
You don't mention which version of the tools you are using so I will use version 2018.2 as an example.
The minimum version of IES that you can use with any version of Vivado is specific and documented in User Guide 973 e.g. for Vivado 2018.2 the minimum version is 15.20.042
You will also need to compile the libraries in order for IES to work with the Xilinx IP.
You can do this in Vivado from Tools -> Compile Simulation Libraries, this only has to be done once per version of Vivado/Simulator version as the libraries can be shared.
Once this is done you can run simulation in IES either from the GUI or from a script.
To export the script type
export_simulation -simulator IES -directory ./path_to_store_script -lib_map_path /path_to_where_libraries_are
This will give you a script that will run the simulation without having to launch Vivado, you can also check it for the files used to compile.