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Registered: ‎05-22-2018

Using PLL output in a process sensitivity list does not work

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Hi everyone,

 

I am using Xilinx ISE 13.2 and for my current work, I am trying to use a PLL output in a sensitivity list of process. I am feeding a 200 MHz differential clock to the top module, which is routed to PLL. The PLL gives an output single-ended clock of 50 MHz which I am trying to use in the sensitivity list. However, I do not see the output change based on this derived clock. 

To explain the problem, I attached codes for a 5-bit counter and the corresponding test bench , that uses a derived clock from the PLL in its sensitivity list (counter.vhd and counter_tb1.vhd). The use of the derived clock is more or less the same in the actual application too.

with_PLL.PNG

Also following is the simulation output for without PLL (counter_without_PLL.vhd and counter_tb.vhd)

without_PLL.PNG

 

Can someone suggest why the counter value does not increment on edge of the derived clock signal as mentioned in the code? How do I get the code with PLL to work?

 

Thanks in advance,

 

 

-Chandrasekhar DVS

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307 Views
Registered: ‎05-22-2018

Hi @dpaul24 ,

 

Thanks for that. However that was only simulation problem. I was using a single ended PLL output clock while giving a differential clock as input. When I created the simulation test bench, both the 'p' and 'n' ends were identically defined in test bench that was not giving out the PLL output and hence, no result observed.

It should not be a problem when I program the board as PLL would be correctly implemented there.

The problem was that I am assigning default values to input ports of top module and expecting to see the output. I saw on one of the forum posts that it should be fine (the input ports WOULD take the default values assigned while defining the entity), which did not happen.

entity name is

port(

p1: in std_logic_vector(7 downto 0):= "00101101";

p2: in std_logic_vector(7 downto 0):= "11010010";

p3: out std_logic_vector);

end name;

 

architecture logic of name is

begin

process(clk)

begin

  if(p1 = "001001101" and p2 = "11010010") then

     --do something

     p3<= '1';

  end if;

end logic;

Hence for initial testing I used internal signals as source and everything worked fine.

entity name is

port(

);

end name;

 

architecture logic of name is

signal p1: std_logic_vector(7 downto 0):= "00101101";

signal p2: std_logic_vector(7 downto 0):= "11010010";

begin

process(clk)

begin

  if(p1 = "001001101" and p2 = "11010010") then

     --do something

     p3 <= '1';

  end if;

end logic;

Thanks for attending the question though!

 

-Chandrasekhar DVS

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Scholar
Scholar
392 Views
Registered: ‎08-07-2014

@krishnachandrasekhar100 ,

I can see 1 basic problem, the pll_locked does not go to HIGH.

PLL will output valid clock only when pll_locked is '1'. You should use the clock output from the PLL only after pll_locked is '1'. Make this RTL change.

Possible solution: It takes some time for the locked signal to go HIGH. How long did you run the simu? Try running it longer to see is it is going HIGH.

 

------------FPGA enthusiast------------
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308 Views
Registered: ‎05-22-2018

Hi @dpaul24 ,

 

Thanks for that. However that was only simulation problem. I was using a single ended PLL output clock while giving a differential clock as input. When I created the simulation test bench, both the 'p' and 'n' ends were identically defined in test bench that was not giving out the PLL output and hence, no result observed.

It should not be a problem when I program the board as PLL would be correctly implemented there.

The problem was that I am assigning default values to input ports of top module and expecting to see the output. I saw on one of the forum posts that it should be fine (the input ports WOULD take the default values assigned while defining the entity), which did not happen.

entity name is

port(

p1: in std_logic_vector(7 downto 0):= "00101101";

p2: in std_logic_vector(7 downto 0):= "11010010";

p3: out std_logic_vector);

end name;

 

architecture logic of name is

begin

process(clk)

begin

  if(p1 = "001001101" and p2 = "11010010") then

     --do something

     p3<= '1';

  end if;

end logic;

Hence for initial testing I used internal signals as source and everything worked fine.

entity name is

port(

);

end name;

 

architecture logic of name is

signal p1: std_logic_vector(7 downto 0):= "00101101";

signal p2: std_logic_vector(7 downto 0):= "11010010";

begin

process(clk)

begin

  if(p1 = "001001101" and p2 = "11010010") then

     --do something

     p3 <= '1';

  end if;

end logic;

Thanks for attending the question though!

 

-Chandrasekhar DVS

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Registered: ‎08-07-2014

@krishnachandrasekhar100 ,

The target is to make simulation as much as possible close to real life operation.

Assigning default values to ports is discouraged, although it is not wrong. You second part of the code is much better.

There is still a but! You can always change those values through test-bench stimulus. I would have the default values set for p1 and p2 to be "00000000" during their declarations. Then from the test bench you should toggle the inputs p1 and p2 and observe what happens to p3.

 

------------FPGA enthusiast------------
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