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rikusleroux
Explorer
Explorer
4,708 Views
Registered: ‎05-21-2009

Using UNISIM components in Questa

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Hi guys,

 

I'm having some issues with Questa Sim. I'm trying to simulate a design with BUFG and DCM components. The following library declarations exist in my top level design as well as in my testbench:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all ;
use IEEE.std_logic_textio.all; 
use std.textio.all ;



library UNISIM;
use UNISIM.all;
use UNISIM.vcomponents.all;

 

However, I get the following errors when synthesizing in Questa:

 

"Identifier "BUFG" is not directly visible." and "Identifier "DCM_BASE" is not directly visible."

 

The UNISIM library is available and compiled in Questa (I see it under the libraries-tab). Why are these components not directly visible? I have an ICAP instantiates as well and this seem to simulate correctly. What am I doing wrong?

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graces
Moderator
Moderator
5,951 Views
Registered: ‎07-16-2008

Try removing "use UNISIM.all".

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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2 Replies
graces
Moderator
Moderator
5,952 Views
Registered: ‎07-16-2008

Try removing "use UNISIM.all".

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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rikusleroux
Explorer
Explorer
4,696 Views
Registered: ‎05-21-2009
Hi graces, Thanks a lot! That worked like a charm. Why did that cause a problem? Are the component-libraries included multiple times by UNISIM.all and UNISIM.vcomponents? Why can't I just include UNISIM.all since vcomponents are inluded by "alll"?
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