07-23-2018 01:29 PM
I am using Vivado 2017.4 and I have no third party simulator. I have been trying to create a testbench using UVM and have been unsuccessful. I have read many posts on the subject, and some that said Vivado doesn't support UVM. However, I downloaded the UVM library from accelera's website and looked at the code and it looks like it's just some SystemVerilog. I have tried to import it into my project and it seems like the errors were from a wrong compilation order: "uvm_object is not declared", "uvm_barrier is already declared", etc. Is there any way to compile the UVM code properly and use it in a testbench? Or what would be the cheapest simulation tool that supports UVM? Also, is Xilinx planning to support UVM within Vivado in the (near) future?
07-24-2018 04:04 AM
UVM is a methodology with a class library written entierly in SystemVerilog. The SV support in Vivado simulator is not complete and so UVM wont be possible in it any time soon.
Also, afaik, UVM support is not normally a feature on base level simulator licences (you may be able to compile it yourself though). You normally need to use a more expensive licence for decent UVM support.
07-29-2020 03:49 AM - edited 07-29-2020 05:54 AM
two years have passed, I wonder if Vivado is now capable of basic UVM.
I tried this in Vivado version 2020.1 and failed:
program automatic test_program;
import uvm_pkg::*; initial begin `uvm_info("DEMO", "Hello World!", UVM_MEDIUM); end endprogram
uvm_info is seen as an undefined macro.
However, the code editor has no problem with uvm_pkg::*; but it does have a problem with uvm_abcdef_pkg::*; so I guess there must some uvm_pkg already there.