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Visitor aimatee
Visitor
1,075 Views
Registered: ‎02-24-2018

Using VCS to simulate vivado design

Hi,

 

I am trying to use VCS to simulate a vivado design. I compiled simulation library for VCS from Vivado and did export_simulation.

 

Everything seems fine expect that an error showed up during elaboration.

 

Error-[SFCOR] Source file cannot be opened
  Source file "xil_defaultlib.tb_myAXI4IP" cannot be opened for reading due to
  'No such file or directory'.
  Please fix above issue and compile again.

 

I didn't see an error in the vlogan compilation log. Why didn't 'tb_myAXI4Ip' get generated in xil_defaultlib? I only see a 'AN.DB' folder under xil_defaultlib.

 

Attached are the simulation script, vlogan compilation log and elaboration log.

 

Many thanks!

 

 

 

 

 

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Visitor aimatee
Visitor
1,013 Views
Registered: ‎02-24-2018

Re: Using VCS to simulate vivado design

I found the problem.

 

The issue was that I used vcs instead of vcs-mx. My source codes contain systemverilog and verilog.

 

Once I change my VCS_HOME to use vcs-mx, it worked fine.

 

Thanks.