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Explorer
Explorer
4,676 Views
Registered: ‎04-23-2013

Using a procedure to simulate bus reads and writes in a testbench

I have a simple control bus in my VHDL module that has a data bus and a control/address bus.

It is written to by setting the data, address and direction and then toggling a strobe bit.

 

I want to use a procedure in my testbench to perform reads and writes on this control bus, mainly so that the code is more readable.

I read that " Procedures are more general than functions, and may contain timing controls." in VHDL-lab4.pdf

 

So I wrote a procedure and it is compiling.

It forced me to use variables for the outputs.

However, I don't know how to permanently assign the variables to the signal_vector inputs to the uut.

 

Please help.

Thanks,

Emmett

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2 Replies
Explorer
Explorer
4,648 Views
Registered: ‎09-13-2011

Re: Using a procedure to simulate bus reads and writes in a testbench

It is a matter of scope. If you put the procedure into the stim_proc process at line 620 you can use signals directly - you can work on all signals set in that process.

For example:

            -- Read Reg Procedure
            -- Expecting 8-bit address aligned to 8-bit
            procedure CFReadReg (
                Address         : in    std_logic_vector(19 downto 0);
                signal Data     : out   std_logic_vector(7 downto 0)
                ) is
            begin  
                AV_in <= Address;
                nVMEMWE_in <= '1';    
                wait for ClkPeriod80MHz;
                nVCS1_in <= '0'; 
                nVMEMOE_in <= '0';     
                wait for ClkPeriod80MHz * 4;
                Data <= DV_inout;
                wait for ClkPeriod80MHz;
                nVMEMOE_in <= '1';
                nVCS1_in <= '1'; 
                wait for ClkPeriod80MHz;
                AV_in <= (others => '0');
                wait for ClkPeriod80MHz;
            end CFReadReg;

 

Explorer
Explorer
4,641 Views
Registered: ‎04-23-2013

Re: Using a procedure to simulate bus reads and writes in a testbench

Worked like a charm!

Thanks,

Emmett

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