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tessitd
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Registered: ‎11-13-2009

Using +arg to control data files used inside a testbench

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All,

 

I am using both QuestaSim and XSIM for a project.  In QuestaSim we do the following:

 

vsim work.data_test -do "run -all; quit;" +IOFILE=sample_data_file

 

So we just run the simulation and capture the logs.  But the part that isn't working with XSIM is the +IOFILE=sample_data_file.

 

In our simulation environment we have a test framework that sets the design up, applies the IOFILE, collects the results, scores the results and report status.

 

The IOFILE is constantly changing as the design is data centric and we don't need to create a bunch of new tests when it is really the data file which is changing.

 

So How do I do the +ARG=VALUE in XSIM?

TomT...

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tessitd
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Registered: ‎11-13-2009

@amaccre

 

Well I have uncovered what the issue is.  You are talking about how to pass a top level PARAMETER to a SystemVerilog module. I was talking about how to use the common Verilog approach called "+args" which is NOT a Parameter.  This is a method that has been used for decades to pass options into Verilog.

 

So the correct technique to seen in a "+arg" (aka PLUSARGS) is to use add it to the simulation command line by using the command:

 

set_property -name {xsim.simulate.xsim.more_options} -value {+IQFILE=text1} -objects [get_filesets sim_1]

 

As an example.  This can also be set in the GUI using the Flow-> Settings -> Simulation Settings and the Simulation Tab.

 

That is the proper way to get the "+arg" into the simulator.

TomT...

 

 

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amaccre
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Registered: ‎04-24-2013

Hi @tessitd,

 

If you want to pass Generics / Parameters to XSim then you can do so in the following way:

 

-generic {IOFILE sample_data_file.dat} 

 

or set it in the gui

 

 

Capture_sim.PNG

 

Best Regards
Aidan

 

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tessitd
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Registered: ‎11-13-2009

Aidan,

 

So if I wanted to TCL script this up do you have a suggestion?

 

What we are doing is running the sample test on multiple DATA files, the error status from the simulation is what we using for scoring as we have a Scoreboard that can tell if the test was successful.

 

So this TCL loop would call the simulator multiple times changing the generic and then reviewing the simulation status.

 

Thanks,

TomT...

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tessitd
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Registered: ‎11-13-2009

Aidan,

 

Well that didn't entirely work; it fails on elaboration so I thought I would put some code snippets here for your review and tell me how to get this +ARG into the simulator.

 

So here is the Error from the elaborate.log:

 

Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /apps/Tools/Xilinx/Vivado/2017.4/bin/unwrapped/lnx64.o/xelab -wto e30db835f91644b5a6eefe65c27e9b0a --incr --debug typical --relax --mt 8 -generic_top IQFILE=simple_pulse_train_1a -L xil_defaultlib -L dpu_dbi_lib -L xbip_utils_v3_0_8 -L axi_utils_v2_0_4 -L xbip_pipe_v3_0_4 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_4 -L xbip_bram18k_v3_0_4 -L mult_gen_v12_0_13 -L floating_point_v7_0_14 -L xbip_dsp48_mult_v3_0_4 -L xbip_dsp48_multadd_v3_0_4 -L div_gen_v5_1_12 -L fifo_generator_v13_2_1 -L c_reg_fd_v12_0_4 -L xbip_addsub_v3_0_4 -L c_addsub_v12_0_11 -L xbip_dsp48_acc_v3_0_4 -L xbip_accum_v3_0_4 -L c_accum_v12_0_11 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot sample_data_test_behav xil_defaultlib.sample_data_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
ERROR: [XSIM 43-3281] Parameter/Generic IQFILE  specified in commandline not found in design.

Now I know that in Verilog that the argument should look like +arg=value so I changed the generic and tried again:

 

Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /apps/Tools/Xilinx/Vivado/2017.4/bin/unwrapped/lnx64.o/xelab -wto e30db835f91644b5a6eefe65c27e9b0a --incr --debug typical --relax --mt 8 -generic_top +IQFILE=simple_pulse_train_1a -L xil_defaultlib -L dpu_dbi_lib -L xbip_utils_v3_0_8 -L axi_utils_v2_0_4 -L xbip_pipe_v3_0_4 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_4 -L xbip_bram18k_v3_0_4 -L mult_gen_v12_0_13 -L floating_point_v7_0_14 -L xbip_dsp48_mult_v3_0_4 -L xbip_dsp48_multadd_v3_0_4 -L div_gen_v5_1_12 -L fifo_generator_v13_2_1 -L c_reg_fd_v12_0_4 -L xbip_addsub_v3_0_4 -L c_addsub_v12_0_11 -L xbip_dsp48_acc_v3_0_4 -L xbip_accum_v3_0_4 -L c_accum_v12_0_11 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot sample_data_test_behav xil_defaultlib.sample_data_test xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
ERROR: [XSIM 43-3281] Parameter/Generic +IQFILE  specified in commandline not found in design.

Notice that in the second case the argument is now: +IQFILE=simple_pulse_train_1a

 

Now here is the code snippet that is in the Very Top Level Test:

 

      void'($value$plusargs("IQFILE=%s", iq_file));

      if ($value$plusargs("QUESTASIM=%b", questasim)) begin
         $display("**** Using QuestaSim ****");
         // change path if using QuestaSim
         $sformat(pdw_file, "../tb/data/%0s.pdw", iq_file);
         $sformat(iq_file, "../tb/data/%0s.txt", iq_file);
      end else begin
         $display("**** Using Vivado Sim *****");
        $sformat(pdw_file, "test.pdw", iq_file);
        $sformat(iq_file, "test.txt", iq_file);
        // FIXUP THIS ISNT WORKING IN Vivado!
        // $sformat(pdw_file, "%0s.pdw", iq_file);
        // $sformat(iq_file, "%0s.txt", iq_file);
      end

This is a standard Verilog way to use the +args so how do I make XSIM accept this data?

TomT...

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tessitd
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Registered: ‎11-13-2009

Any thoughts on how to get this to work.  The -generic {IQFILE filename.dat} didnt work!

 

TomT...

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patocarr
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Registered: ‎01-28-2008
It seems you're expecting the generic to be "IQFILE", but the OP said "IOFILE".

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tessitd
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Registered: ‎11-13-2009

Please review the Logs and the Sample SystemVerilog code.  The Verilog +args does show up on the Simulation Command line and  I tried two different approaches:

 

1) IQFILE=test.dat

 

2) +IQFILE=test.dat

 

Neither approach worked in Simulation.  Which is the problem.

 

This is STILL NOT WORKING -- so any assistance?

 

TomT...

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amaccre
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Registered: ‎04-24-2013

Hi @tessitd,

 

When you post a reply it is useful to include the @ version of the persons name e.g. @amaccre, this way the person is notified.

Without this then it can look as if there is no response and issues can be missed.

 

Taking the bft example provided with Vivado as a working project for this, there is a Verilog parameter in the test bench called READ_PERIOD. If you want to pass a value to this then you can do so either from the GUI or from the command line in the following way.

 

Param.PNG

 

From the screen shot you can see that the value was set to 10 and this is replicated in the command that is issued when running the simulation: -generic_top READ_PERIOD=10

 

When the READ_PERIOD is set to 10, you can see the clock is changing on multiples of 10

 

RP10.PNG

 

When the READ_PERIOD is set to 8, you can see the clock is changing on multiples of 8

 

RP8.PNG

 

Also as per User Guide 900

 

Generics (Parameters) Mapping
The Vivado simulator supports the following VHDL generic types (and their Verilog/SV equivalents):
• integer
• real
• string
• boolean
Note: Any other generic type found on mixed language boundary is considered an error.

 

Looking at you original post, the parameter you referenced was was IOFILE:

 

vsim work.data_test -do "run -all; quit;" +IOFILE=sample_data_file

 

But In you error message it is called IQFILE

 

ERROR: [XSIM 43-3281] Parameter/Generic IQFILE  specified in commandline not found in design.

Is there a mismatch in your code?

 

Best Regards
Aidan

 

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tessitd
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Registered: ‎11-13-2009

Please see the code snippets and the output of the simulator.  The mismatch was in my original posting!  Does a String need to be enclosed in quotes?

 

TomT...

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tessitd
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Registered: ‎11-13-2009
@amaccre, The mismatch was in my original posting. Does a STRING need to be quotes? Please review the code snippets and the output of the log. I did indeed use the GUI to set up these parameters as you can see in the output of the logs I provided.
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amaccre
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Registered: ‎04-24-2013

Hi @tessitd,

 

No the string doesn't have to be in inverted commas / quotes.

 

Here is the xelab command generated by the GUI with the two paramaters set.

 

xelab.exe -wto 2e683ed0490a4b0c847fd5dff18952c7 --incr --debug typical --relax --mt 2 -generic_top READ_PERIOD=10 -generic_top IQFILE=filedata.txt -L xil_defaultlib -L bftLib -L unisims_ver -L unimacro_ver -L secureip --snapshot bft_tb_behav xil_defaultlib.bft_tb xil_defaultlib.glbl -log elaborate.log

 

Here is where I set them in the GUI under Simulation Settings

 

IQFIle.JPG

 

And here is the result in the Simulation, you can see that the IQFILE parameter has been changed from file1.txt in the code to filedata.txt as passed by the tools.

 

IQFIle1.JPG

Best Regards
Aidan

 

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tessitd
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Registered: ‎11-13-2009

@amaccre

 

Well I have uncovered what the issue is.  You are talking about how to pass a top level PARAMETER to a SystemVerilog module. I was talking about how to use the common Verilog approach called "+args" which is NOT a Parameter.  This is a method that has been used for decades to pass options into Verilog.

 

So the correct technique to seen in a "+arg" (aka PLUSARGS) is to use add it to the simulation command line by using the command:

 

set_property -name {xsim.simulate.xsim.more_options} -value {+IQFILE=text1} -objects [get_filesets sim_1]

 

As an example.  This can also be set in the GUI using the Flow-> Settings -> Simulation Settings and the Simulation Tab.

 

That is the proper way to get the "+arg" into the simulator.

TomT...

 

 

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