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jsmithsrc
Adventurer
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Registered: ‎06-25-2012

Using output of export_simulation with Riviera for compilation of IP libraries

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I have a Vivado Project with an IPI block diagram. I am attempting to utilize export_simulation in order to export source files and compilation script (compile.do) so I can create libraries to utilize with Riviera.

 

Setup:

  • Vivado 2016.2
  • Riviera 2015.10
  • Simulation Language set to VHDL
  • Design validates, and all output products have been generated, OOC per IP

From what I gather, from the release notes of 2016.2, this is the Xilinx supported combination of tools.

 

The export process appears to work correctly, but the compilation script does not work. Specifically, I see the following in the compile.do file:

 

# Creating Libraries <omitted>
... # Mapping libraries <omitted>
... vlog -work xil_defaultlib -v2k5 -sv "+incdir+<omitted> \ "srcs/xpm_cdc.sv" \ "srcs/xpm_memory_base.sv" \ "srcs/xpm_memory_dpdistram.sv" \ "srcs/xpm_memory_dprom.sv" \ "srcs/xpm_memory_sdpram.sv" \ "srcs/xpm_memory_spram.sv" \ "srcs/xpm_memory_sprom.sv" \ "srcs/xpm_memory_tdpram.sv" \

This line does not work. It appears to be a syntax related issue. I get many verilog compilation errors, some of which are similar to the following line:

ALOG: Error: VCP1004 <path omitted>/xpm_cdc.sv : (179, 116): String constant is not closed by double quote.

I took a look to see what the two flags mean.

  • Flag -v2k5: Forces the compiler to conform to IEEE Std 1364™-2005. SystemVerilog extensions are not allowed.
  • Flag -sv: This flag is not documented, but I don't see alog rejecting the flag outright (perhaps it is a legacy flag?)

As a possible work-around, I tried the -sv2k5 flag instead of -v2k5 and -sv. The number of errors were reduced, and now have errors like:

ALOG: Error: VCP2000 <path omitted>/xpm_cdc.sv : (190, 5): Syntax error. Unexpected token: action block statement.

When using -sv2k9 flag, compilation seems to get further, but ultimate dies with cryptic message:

ALOG: Error: VCP0120 Internal unknown error occurred.

For reference, the export_simulation command I am using looks something like this:

export_simulation -simulator riviera -absolute_path -32bit -directory <path omitted>/vivado_export_ip/ -lib_map_path <path omitted>/simlib/2016.2_R2015.10_32/library.cfg -of_objects [get_files core.bd] -export_source_files -force -use_ip_compiled_libs

Another issue I have been having, which I am not sure if it is related or not, is referencing the IP compiled libraries (generated with compile_simlib) does not seem to have any effect on the output scripts. I can't find any reference to these libraries in the output files. This causes issues during VHDL compilation (which follows after the failing verilog compilation in the compile.do script). I have tried both specifying the directory containing libraries and the library.cfg file itself, neither of which seems to have any effect.

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jsmithsrc
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Registered: ‎06-25-2012

After consulting with Aldec, I have confirmed that the sv files in question can be successfully compiled with 2016.06 version of their product.

 

To compile successfully, I needed to use the flag -sv2k9 instead of -v2k5 -sv

View solution in original post

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vemulad
Xilinx Employee
Xilinx Employee
8,564 Views
Registered: ‎09-20-2012

Hi @jsmithsrc

 

The xpm related files need not be compiled, you can remove them from the script file.

Thanks,
Deepika.
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jsmithsrc
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Registered: ‎06-25-2012

Can I expect that the xpm files will not be exported in the future, then? e.g. this is a bug that needs to be fixed?

 

It is inconvenient to have to manually remove these files from compilation script. I was hoping to use a scripted flow to first export sources from vivado and then run the exported compile.do in Riviera without intervention.

 

Any thoughts on the second issue? That the pre-compiled libraries (e.g. UNISIM) are not being mapped in prior to the compilation process as part of the script?

 

 

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vemulad
Xilinx Employee
Xilinx Employee
8,554 Views
Registered: ‎09-20-2012

Hi

 

Yes, there is a CR already in place to remove xpm related files in the generated scripts.

 

Regarding your second query, refer to page-129 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug900-vivado-logic-simulation.pdf

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
jsmithsrc
Adventurer
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8,545 Views
Registered: ‎06-25-2012

Thanks, I see that library.cfg (used by Riviera) is generated by the compilation of simulation libraries feature.

 

Do I need to manually reference this with Riviera when using compile.do?

If so, what function does -lib_map_path and -use_ip_compiled_libs arguments to export_simulation serve?

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jsmithsrc
Adventurer
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15,511 Views
Registered: ‎06-25-2012

After consulting with Aldec, I have confirmed that the sv files in question can be successfully compiled with 2016.06 version of their product.

 

To compile successfully, I needed to use the flag -sv2k9 instead of -v2k5 -sv

View solution in original post

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vijayak
Xilinx Employee
Xilinx Employee
8,309 Views
Registered: ‎10-24-2013

Hi @jsmithsrc

 

Thanks for posting the answer. Please close the thread by marking the solution in the interest of other users.

PS: We suggest the customers to contact Aldec (which is mentioned in the release notes.) for issues related to Riviera.

 

Thanks,Vijay
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