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mu_guang
Visitor
Visitor
552 Views
Registered: ‎11-10-2020

VCS compiles XILINX FIFO IP gets

When I using VCS o-2018.09-SP2 compile FIFO and RAM ,it gets wrong message, but compiling the  ADD.hdl and SUB.hdl has no error 

the shell is 

SELF_IP=/home/fpga-0/NGS_prj/UVM/matrix7_uvm/rtl/lib/self_iplib
NOVAS_HOME=/home/fpga-0/software/synopsys2018/verdi_2018.09
compile:
vhdlan \
-full64 \
-nc \
${NOVAS_HOME}/share/PLI/VCS/LINUX64/novas.vhd \
${SELF_IP}/ADD.vhd \
${SELF_IP}/SUB.vhd \
${SELF_IP}/fifo_512x512.vhd \
${SELF_IP}/fifo_512x16.vhd \
${SELF_IP}/ram_2port_512x32_4096x4.vhd \

the error message is 

Error-[OVNOSELECT1_LIB] Undefined identifier
/home/fpga-0/NGS_prj/UVM/matrix7_uvm/rtl/lib/self_iplib/fifo_512x512.vhd, 57
FIFO_512X512

USE fifo_generator_v13_2_3.fifo_generator_v13_2_3;
^
The symbol named 'FIFO_GENERATOR_V13_2_3' cannot be found in library
'FIFO_GENERATOR_V13_2_3'.


Error-[IEEEVHDLNOENT] Missing compiled design unit
/home/fpga-0/NGS_prj/UVM/matrix7_uvm/rtl/lib/self_iplib/fifo_512x512.vhd, 74
analysis-Parsing, "FIFO_512X512"

ARCHITECTURE fifo_512x512_arch OF fifo_512x512 IS
^
The compiled design unit for entity 'FIFO_512X512' is not found in WORK
library.
Please verify that the entity was analyzed successfully.

"/home/fpga-0/NGS_prj/UVM/matrix7_uvm/rtl/lib/self_iplib/fifo_512x512.vhd": errors: 2; warnings: 0.
Parsing design file '/home/fpga-0/NGS_prj/UVM/matrix7_uvm/rtl/lib/self_iplib/fifo_512x16.vhd'

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2 Replies
harikade
Xilinx Employee
Xilinx Employee
474 Views
Registered: ‎05-01-2019

Hi,

The error "The symbol named 'FIFO_GENERATOR_V13_2_3' cannot be found in library
'FIFO_GENERATOR_V13_2_3'." says that the IP library FIFO_GENERATOR_V13_2_3 is not available. Please check your synopsys_sim.setup file. It should have the mapping for required dependency libraries.

Thanks,

Harika.

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mu_guang
Visitor
Visitor
422 Views
Registered: ‎11-10-2020

I have check the synopsys_sim.setup file, and the library mapped to 

>fifo_generator_v13_2_3 : /home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3

the path contained file like

/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.verilog.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.cmd
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.verilog.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.cmf
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.verilog.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.rpt
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.vhdl.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.cmd
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.vhdl.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.cmf
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.vhdl.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.rpt
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64/.vhdl_lib_lock
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64/vhdl.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64/vhmra.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/.vcs_lib_lock
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/AllModulesSkeletons.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/compat.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/debug_dump
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/dumpcheck.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/dve.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/make.vlogan
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/modfilename.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/str.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/str.index.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/str.info.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/vir.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/vir_global.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/vloganopts.db

but the error stll exist, I have no idea about the error, looking for your suggestion

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