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Participant diegosantibanez
Participant
282 Views
Registered: ‎07-25-2017

VHDL Complex adder problem

Hello,

 

I'm trying to create a simple Complex_sum block in VHDL.

My inputs are 2 AXIS (32 bits -> 16 bits for reals, 16 bits for imag), and my output is 1 AXIS (32 bits -> 16 bits for reals, 16 bits for imag).

I deal with bit growth by truncating 1 bit:

 

sum_result_r_A <= resize(tdata_reg_0_r, sum_result_r_A'length)+resize(tdata_reg_1_r, sum_result_r_A'length);
sum_result_i_A <= resize(tdata_reg_0_i, sum_result_i_A'length)+resize(tdata_reg_1_i, sum_result_i_A'length);

sum_result_A(((C_S00_AXIS_TDATA_WIDTH/2))-1 downto 0) <= sum_result_r_A(((C_S00_AXIS_TDATA_WIDTH/2)+trunc)-1 downto 0+trunc);
sum_result_A((C_S00_AXIS_TDATA_WIDTH)-1 downto (C_S00_AXIS_TDATA_WIDTH/2)) <= sum_result_i_A(((C_S00_AXIS_TDATA_WIDTH/2)+trunc)-1 downto 0+trunc );

 

 

When I simulate this, everything is correct, but if I run post-Implementation Functional simulation, there is a missmatch.

My output range should be  -2^(15)  to (2^15)-1 for both real and imag parts, as I'm working with signed values.

However, If I try to add values over 2^14, last bit is changed and values are wrong.

For example, if I try to add 32000 + 32000:

Simulation result:

32000 + 3200 = 64000/2(1 bit truncate) = 32000 [7d00]

Post Implementation simulation result:

32000 + 32000 =  -768 [FD00]  (last bit is wrong)

 

 

I guess it has something to do with resize function, but I don't really know what's going on.

Any idea?

 

Thanks!

 

 

 

 

 

 

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