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Adventurer
Adventurer
12,487 Views
Registered: ‎09-30-2014

VHDL Falling_edge, in detail

Dear forum,

 

I faced a surprising situation while writing reactive VHDL code for Vivado 2014.4 simulator use, where

 

qqq'event and '0' = qqq is true;

 

'1' = qqq'last_value and '0' = qqq is true;

 

but  falling_edge(qqq) is false.

 

(signal qqq: std_logic is in the sensitivity list of current process, not altered by the process failing to see the falling_edge)

 

Just looking at the simulator traces, the signal makes a plain normal one-to-zero transition.

 

To my knowledge, falling_edge should be true when there is event, last value is one and value is zero.

 

What have I missed? What is needed for a falling edge in addition to event, last_value=one, and value=zero?

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7 Replies
Xilinx Employee
Xilinx Employee
12,471 Views
Registered: ‎09-13-2014

Re: VHDL Falling_edge, in detail

Your check is correct and I am expecting falling_edge to return TRUE but as it's not happening in your case, I would suggest to do following

 

1> Have you included any other package apart from std_logic_1164? If yes, then what are those and if it contain any uder defined package then you may check if those package contains any overloaded form of falling_edge or not

2> You can check one more thing by writing following piece of code in process which is sensitive to qqq

 

process(qqq)

begin

    report "value of signal qqq at last event was "&std_logic'image(qqq'last_event)& " and at present is "&std_logic'image(qqq);

  report boolean'image(qqq'event and (To_X01(qqq) = '0') AND (To_X01(qqq'LAST_VALUE) = '1'));

end process;

 

And share the o/p. If it's still showing FALSE then would like to see your design as I am suspective some race condition(unlikely) or wrong usage(very likely).

 

--dhiRAj

Adventurer
Adventurer
12,455 Views
Registered: ‎09-30-2014

Re: VHDL Falling_edge, in detail

Hi, dprasad,

 

Thanks for the quick answer.

1) I am including ieee.std_logic_arith in addition to ieee.std_logic_1164.

2) Are you sure you wanted last_event? I took the liberty to add last_value to the above code, resulting the following:

 

process (qqq)
  begin
    report "value of signal qqq at last event "&time'image(qqq'last_event)& " was " & std_logic'image(qqq'last_value) &" and at present is "&std_logic'image(qqq);
    report "qqq " & boolean'image(qqq'event and (To_X01(qqq) = '0') AND (To_X01(qqq'LAST_VALUE) = '1'));
    report "qqq-cont " & boolean'image(falling_edge(qqq));
  end process;

 

The reports are:

 

Note: value of signal qqq at last event 0 ps was '1' and at present is '0'
Note: qqq true
Note: qqq-cont false


The project with a problem is rather large. So-far I have not able to extract the problem into a small-enough chunk that could be posted to this forum. I too find an "user error" to be a possible cause, but I do not have the tools to proceed.

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Xilinx Employee
Xilinx Employee
12,448 Views
Registered: ‎09-13-2014

Re: VHDL Falling_edge, in detail

Very surprising as both 

 

report "qqq " & boolean'image(qqq'event and (To_X01(qqq) = '0') AND (To_X01(qqq'LAST_VALUE) = '1'));
report "qqq-cont " & boolean'image(falling_edge(qqq));

 

are interanally same. 

 

Even if it's big design, will it be possible to share that. I can look at it. I am suspecting something very simple thing is going on which we are not able to foresee.

 

--dhiRAj

Adventurer
Adventurer
12,442 Views
Registered: ‎09-30-2014

Re: VHDL Falling_edge, in detail

This is not a hobby project; sharing it with a "nice guy at the internet" might be bureaucratically challenging. I appreciate your help a lot despite these restrictions!

 

For the sake of better understanding, I copied the falling-edge function from Vivado/2014.4/data/vhdl/src/ieee/distributable/std_logic_1164.vhd into a locally-defined "phalling_edge". The outcome of this test was that phalling_edge was also true, falling_edge still remained false.

 

I cannot find any refefinitions of falling_edge. There are, however, some encrypted IP blocks in use elsewhere in the project. Is there a way to query Vivado regarding where has it picked the falling_edge in use from??

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Xilinx Employee
Xilinx Employee
12,435 Views
Registered: ‎09-13-2014

Re: VHDL Falling_edge, in detail

In VHDL, we don't have any concept of dumping hierarchy. I tried very simple example like

_____________

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity top is
end entity top;

architecture arch of top is
signal s1 : std_logic;
begin
process(s1)
begin
report "value at time "&time'image(now)& " "&boolean'image(falling_edge(s1));
end process;
process
begin
s1 <= '1';
wait for 1ns;
s1 <= '0';
wait for 1ns;
s1 <= '1';
wait for 1ns;
s1 <= '0';
wait for 1ns;
s1 <= '1';
wait for 1ns;
s1 <= '0';
wait for 1ns;
s1 <= '1';
wait for 1ns;
s1 <= '0';
wait for 1ns;
wait;
end process;
end;

___________

and it's working fine.  One thing you can do is by replacing falling_edge with absolute name i.e

 

ieee.std_logic_1164.falling_edge

 

and see if it's working.  This will remove the confusion about if the function is mapped to any different package.

 

--dhiRAj

 

 

Adventurer
Adventurer
12,429 Views
Registered: ‎09-30-2014

Re: VHDL Falling_edge, in detail

Hi again! I am really impressed by the speed at which you answer, and also that you have given many promising tips.

 

.. that being said, printing boolean'image(ieee.std_logic_1164.falling_edge(qqq)) gives the unexpected value.

 

I know that the falling_edge function usually works; also this test bench module works as expected in another project.

 

I sanitized the file a bit and removed the use of std_logic_arith. No effects.

 

If you have more ideas, I gladly try those as well, but even if you do not -- Thanks for everything so far!

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Adventurer
Adventurer
12,418 Views
Registered: ‎09-30-2014

Re: VHDL Falling_edge, in detail

Summary of today's discussions for a casual reader:

 

- I have a problem: falling_edge returns false, despite of an event, and signal going from one to zero

 

- Calling ieee.std_logic_1164.falling_edge( signal name ) unexpectedly returns false, as well.

- Copying the code of falling_edge from Vivado/2014.4/data/vhdl/src/ieee/distributable/std_logic_1164.vhd into a local function results gives the expected result of true.

 

 

Vivado 2014.4, behavioral simulation. Problem repeats, but is not easy to reproduce from scratch.

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