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Observer nagakiranjapan
Observer
260 Views
Registered: ‎05-17-2018

VHDL Hierarchical signal access

I want to access several signals from my testbench that are not part of Top level signals. I am using Vivado 2019.1 and VHDL. I am using the below syntax-

Sig1 <= << signal top_dut.module_inst.sig2 : std_logic >>;

I am getting the error - 

[XSIM 43-3316] Signal SIGSEGV received

I have tried changing the fileproperties to VHDL2008 but to no avail. 

Does Vivado 2019 support hierarchical signal access, and is there any workaround ???

 

 

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3 Replies
Moderator
Moderator
202 Views
Registered: ‎11-09-2015

Re: VHDL Hierarchical signal access

HI @nagakiranjapan 

As you mention, you need to use VHDL2008 to get hierarchical names support.

Did you change the type to VHDL2008? It is not making any changes to the simulation?

Are you sure the call to the hierachical name is the issue? The error [XSIM 43-3316] Signal SIGSEGV received can mean a lot of thing.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Observer nagakiranjapan
Observer
155 Views
Registered: ‎05-17-2018

Re: VHDL Hierarchical signal access

Thanks @florentw,

I am able to access the signal hierarchically.

Seems that the mistake was in not naming the path by taking current module name and proceeding with the instance name down the hierarchy.

Also I have another doubt.

Is it possible to access entity ports rather than the signals of a module. I am getting the class mismatch error in Questasim-

The object class "SIGNAL(driven)" of "TB_TOP.FPGA_INST.u_TOP.sig1" is different from the class "VHDL INPUT PORT" of the denoted object.

I am accessing the input port like this-

<<signal .TB_TOP.FPGA_INST.u_TOP.sig1          : std_logic_vector(NUM-1 downto 0) >>  <=  "11";

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Moderator
Moderator
141 Views
Registered: ‎11-09-2015

Re: VHDL Hierarchical signal access

Hi @nagakiranjapan 

I am not sure, you might want to check first if it is allowed in systemverilog


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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