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dadduni
Observer
Observer
233 Views
Registered: ‎10-08-2020

VHDL Integer overflow and manual reset

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Hi,

I'm experiencing an unusual situation here. I wrote this code.

signal cnt: integer := 0;

process(clk)
if(rising_edge(clk)) then
   Cnt <= cnt +2;
   If(cnt >= 1023) then
      Cnt <= 0;
   end if;
end process;

What I expect is that, because Im using the <= assegnation to signals and not to variables,  the actual value of the signal will be updated at the end of the process and just the last assignement will count.

When cnt is 1022, I expect that the next clk rising edge I will enter the process, I will update the cnt to 1024 after that i will enter in the if and reset the cnt so as output I will ONLY see a 0 and never a 1024.

Is that right?

 

I also expect that this will be synthetized as a 10bit reg and the Elaborated Design seems to do so, but the simulation shows a 1024.

 

Where am I wrong?

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1 Solution

Accepted Solutions
drjohnsmith
Teacher
Teacher
210 Views
Registered: ‎07-09-2009

VHDL is very very very typed.

   You are designing hardware, 

Integers, are of width dependent upon a few things, but  think 32 bits

     they are also signed, 

 

If you want a counter,

    use unsigned , and specify the number of bits you want,

 

Also, 

  Im guessing your getting into VHDL,

      If so , you mention variables, I strongly recommend you not using variables,

           they work different to what you might think as a C programmer, 

 

Have a look at this free book,

   http://freerangefactory.org/

 

BTW: Well done for simulating, that is definitely the way to design HDL , you will spend most of your time in simulation.

 

The reason the simulation shows a different width, is simulation is doing what your code says,

     i.e. 32 bits 

whilst once its elaborated , fitted etc, its been optimised, and the optimiser recognises the top bits are not needed.

 

BTW(2)

    there is / was a school of thought that integers should be used in desings as they simulate faster than std_logic and its derivatives,

      that is still true , but less so,

   the big reason not to use integerrs is they are two levels, 1 or 0, where as in VHDL we have I think 9 levels,

    0 1 H L U X Z ? ?  I can't remember the last 2, if they exist, bu tim certain some one else will , or  look it up.

The reason that 0 1 is not so good, is , what happens when you end up with two outputs driving a net ? std_logic defines what to do , and it shows in simulation, where as the 0 1 

std_logic is called a resolved type, as its always defined what happens when two signals interact.

http://userweb.eng.gla.ac.uk/scott.roy/DCD3/05_Arithmetic.pdf

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

3 Replies
xilinxacct
Instructor
Instructor
215 Views
Registered: ‎10-23-2018

@dadduni 

I think what you are looking for is to assign your intermediate cnt to variable ... then if that variable if above the range assign signal to 0 else assign signal to variable.

Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed.

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drjohnsmith
Teacher
Teacher
211 Views
Registered: ‎07-09-2009

VHDL is very very very typed.

   You are designing hardware, 

Integers, are of width dependent upon a few things, but  think 32 bits

     they are also signed, 

 

If you want a counter,

    use unsigned , and specify the number of bits you want,

 

Also, 

  Im guessing your getting into VHDL,

      If so , you mention variables, I strongly recommend you not using variables,

           they work different to what you might think as a C programmer, 

 

Have a look at this free book,

   http://freerangefactory.org/

 

BTW: Well done for simulating, that is definitely the way to design HDL , you will spend most of your time in simulation.

 

The reason the simulation shows a different width, is simulation is doing what your code says,

     i.e. 32 bits 

whilst once its elaborated , fitted etc, its been optimised, and the optimiser recognises the top bits are not needed.

 

BTW(2)

    there is / was a school of thought that integers should be used in desings as they simulate faster than std_logic and its derivatives,

      that is still true , but less so,

   the big reason not to use integerrs is they are two levels, 1 or 0, where as in VHDL we have I think 9 levels,

    0 1 H L U X Z ? ?  I can't remember the last 2, if they exist, bu tim certain some one else will , or  look it up.

The reason that 0 1 is not so good, is , what happens when you end up with two outputs driving a net ? std_logic defines what to do , and it shows in simulation, where as the 0 1 

std_logic is called a resolved type, as its always defined what happens when two signals interact.

http://userweb.eng.gla.ac.uk/scott.roy/DCD3/05_Arithmetic.pdf

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

drjohnsmith
Teacher
Teacher
126 Views
Registered: ‎07-09-2009

for referance, it was 9 states

https://www.cs.sfu.ca/~ggbaker/reference/std_logic/1164/std_logic.html

I missed "W" and "-",   

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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