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794 Views
Registered: ‎04-30-2019

VHDL compilation fails with Library "unisim" not found

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Hi,

I'm trying to use Questa to simulate and am using the compile_simlib/export_simulation flow.  However, the generated compile.do script fails with a missing unisim library.

Is this a bug or are there steps I'm missing?

1. compile_simlib -force -simulator questasim -directory $::simlib_path -language verilog -family virtexu

2. export_simulation -force -simulator questa -lib_map_path $::simlib_path -directory ./sim/${target}

3. cd ./sim/${target}/questa; vsim -l elaborate.log -batch -do elaborate.do

 

As a side note, the unisims library has been generated in step 1 above.  The directory listing of $::simlib_path is:

drwxrwx--- 13 user group 4.0K Sep 20 15:51 .
drwxrwx---  3 user group 4.0K Sep 20 15:51 ..
drwxrwx---  3 user group 4.0K Sep 20 15:24 common_cpp_v1_0
drwxrwx---  2 user group 4.0K Sep 20 15:22 secureip
drwxrwx---  2 user group 4.0K Sep 20 15:24 simprims_ver
drwxrwx---  2 user group 4.0K Sep 20 15:22 unifast
drwxrwx---  2 user group 4.0K Sep 20 15:23 unifast_ver
drwxrwx---  2 user group 4.0K Sep 20 15:22 unimacro
drwxrwx---  2 user group 4.0K Sep 20 15:23 unimacro_ver
drwxrwx---  2 user group 4.0K Sep 20 15:22 unisim
drwxrwx---  2 user group 4.0K Sep 20 15:23 unisims_ver
drwxrwx---  2 user group 4.0K Sep 20 15:24 xilinx_vip
drwxrwx---  2 user group 4.0K Sep 20 15:24 xpm
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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: VHDL compilation fails with Library "unisim" not found

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The compile_simlib.log looks to be incomplete and no library mapping sections have been added to the modelsim.ini.

In addition, the questasim version in use is incompatible with 2019.1.

WARNING: [Vivado 12-5495] Detected incompatible questasim simulator installation version '2019.2'! The supported simulator version for the current Vivado release is '10.7c'.

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16 Replies
786 Views
Registered: ‎04-30-2019

Re: VHDL compilation fails with Library "unisim" not found

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So I've just found this answer to a previous question:  https://forums.xilinx.com/t5/Simulation-and-Verification/compile-simlib-gt-how-to-import-the-compiled-libraries-to-Questa/m-p/978001/highlight/true#M26056

Ergh, so why isn't this in the documentation?

Secondly, if instead of placing the modelsim.ini in whatever directory you or some member of your team ran the library generation flow, why not place it in the path the libraries are being written to via the '-directory' switch?  That way, when you run the export_simulation stage, it knows where the modelsim.ini is and can set up the scripts correctly.

So what is the solution to this?  I just overwrite the modelsim.ini generated by the export_simulation flow or will that have side effects meaning I have to merge the two?

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: VHDL compilation fails with Library "unisim" not found

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A few issues:

1. unisim is VHDL library. I'd suggest that you run compile_simlib with -language set to all.

2. As you've specified -lib_map_path option in export_simulation, the generated modelsim.ini will be taken into account.

3. To run the generated simulation script, cd to the target directory and run "./xxx.sh".

The main function in the script will do some setup work (e.g. create library mappings) and launch the "compile", "elaborate", "simulate" functions for the 3-step flow.

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Registered: ‎04-30-2019

回复: VHDL compilation fails with Library "unisim" not found

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Hi there,

you're missing the point.  The modelsim.ini isn't in the directory.  When you run 'compile_simlib -directory <path_to_write_libs>', the modelsim.ini is output to the directory where the tool is run from.

It sounds from your answer that this is incorrect so please raise a bug on your team.

Running the shell script fails due to this reason.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: VHDL compilation fails with Library "unisim" not found

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This is not the case at my end. The modelsim.ini is generated in both the pre-compiled library path and the directory from where compile_simlib is launched.

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Registered: ‎04-30-2019

回复: VHDL compilation fails with Library "unisim" not found

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Hi,

find attached a compile log and a tree view of the simlib output directory.  I had to delete it to allow upload.

In the log file you can see this run actually errors out but I'm not sure if that has happened before or not.  The modelsim.ini is written out at the start of the run.

Any idea what is causing this error?  Can you provide an example script with version and host information for me to run to confirm the same behaviour?

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Xilinx Employee
Xilinx Employee
664 Views
Registered: ‎07-16-2008

回复: VHDL compilation fails with Library "unisim" not found

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The compile_simlib.log looks to be incomplete and no library mapping sections have been added to the modelsim.ini.

In addition, the questasim version in use is incompatible with 2019.1.

WARNING: [Vivado 12-5495] Detected incompatible questasim simulator installation version '2019.2'! The supported simulator version for the current Vivado release is '10.7c'.

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643 Views
Registered: ‎04-30-2019

回复: VHDL compilation fails with Library "unisim" not found

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Ah great, another warning that should be an error....

 

thanks.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: VHDL compilation fails with Library "unisim" not found

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Newer release may work, but not guaranteed, as they're not tested. FYI

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632 Views
Registered: ‎04-30-2019

回复: VHDL compilation fails with Library "unisim" not found

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Right, I'll move back to xsim and open a new ticket as that also fails to run.

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Registered: ‎04-30-2019

回复: VHDL compilation fails with Library "unisim" not found

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@graces, I've just got round to installing Questa 10.7c to check out this flow and Vivado still outputs the same warning about 2019.  I've only got 10.7c on my path and it still warns.  What variables does Vivado use to check the executable path?

[shareef@quasar nexysa7]$ echo $PATH | sed -e 's/:/\n/g' | grep mentor
/home/cad/mentor/installs/questa-sim_10.7c/questasim/linux_x86_64

I've attached the log file where I check the path from within Vivado but here is the relevant section:

QUESTA_HOME is set to /home/cad/mentor/installs/questa-sim_10.7c/questasim
'which vlog' returns /home/cad/mentor/installs/questa-sim_10.7c/questasim/linux_x86_64/vlog

and the warning:

WARNING: [Vivado 12-5495] Detected incompatible questasim simulator installation version '2019'! The supported simulator version for the current Vivado release is '10.7c'.

Cheers.

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Xilinx Employee
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Registered: ‎07-16-2008

回复: VHDL compilation fails with Library "unisim" not found

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It's strange that the tool still complains about 2019. Does the compilation proceed and which vlog does it call?

Do you have any other Mentor related environment variable settings? e.g. MODELSIM

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Registered: ‎04-30-2019

回复: VHDL compilation fails with Library "unisim" not found

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Yes it completes fine and generates all required libs.  No other environment variables set.  We use modules to set up the environment for each EDA tool so it's well controlled.

[shareef@quasar electrat-digital]$ env | grep -i mentor
PATH=/home/cad/xilinx/SDK/2019.1/bin:/home/cad/xilinx/Vivado/2019.1/bin:/home/cad/mentor/installs/questa-sim_10.7c/questasim/linux_x86_64:/home/shareef/perl5/bin:/home/shareef/.local/bin:/home/shareef/git/pmu-tools:/home/cad/phozone/latest/bin:/home/shareef/perl5/bin:/home/shareef/.local/bin:/home/shareef/git/pmu-tools:/home/cad/phozone/latest/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/home/shareef/.local/bin:/home/shareef/bin
QUESTA_HOME=/home/cad/mentor/installs/questa-sim_10.7c/questasim
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Xilinx Employee
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Registered: ‎07-16-2008

回复: VHDL compilation fails with Library "unisim" not found

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Looks strange to me. Let me check further and get back to you.

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Xilinx Employee
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Registered: ‎07-16-2008

回复: VHDL compilation fails with Library "unisim" not found

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Would you please send back the output of:

% /home/cad/mentor/installs/questa-sim_10.7c/questasim/linux_x86_64/vcom -version

compile_simlib finds the vcom executable from PATH and then gets the version from the value returned from vcom -version.

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Registered: ‎04-30-2019

回复: VHDL compilation fails with Library "unisim" not found

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[shareef@quasar electrat-digital]$ which vcom
/home/cad/mentor/installs/questa-sim_10.7c/questasim/linux_x86_64/vcom
[shareef@quasar electrat-digital]$ vcom -version
QuestaSim-64 vcom 10.7c_4 Compiler 2019.02 Feb  1 2019
[shareef@quasar electrat-digital]$ 
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Xilinx Employee
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Registered: ‎07-16-2008

回复: VHDL compilation fails with Library "unisim" not found

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It seems the service pack update triggers the warning, as it doesn't match the official 10.7 version.

There'll be an internal discussion on whether we just check the initial version part 10.7c from 10.7c_*.

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