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Participant marco@ms
Participant
12,220 Views
Registered: ‎02-24-2016

VHDL external/hierarchical names support for simulations

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Dear Community,

 

Does Vivado simulator (and ISE) support VDHL external names for simulations?

I spent already quite some time trying to get an answer, but I seem not to be able to find one.

 

My test bench has this line:

 

alias uut_do_dav is <<signal uut.do_dav_mux0 : std_logic>>;

 

and I get the syntax error:

ERROR: [VRFC 10-1412] syntax error near < [C:/Projects/rbp/04_sim/rbp_chirp_dec_tb.vhd:252]

 

I need to access the signal uut.do_dav_mux0 from the testbench, and I can't find a way.

Any help is appreciated

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Participant marco@ms
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20,610 Views
Registered: ‎02-24-2016

Re: VHDL external/hierarchical names support for simulations

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For those who are interested the answer (for Vivado 2015.4) is NO, as you can read from the error message below:

 

ERROR: [XSIM 43-4187] File "C:/Projects/X6/400M/logic/rbp/04_sim/rbp_chirp_dec_tb.vhd" Line 272 : The "Vhdl 2008 External Name" is not supported yet for simulation.

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12 Replies
Moderator
Moderator
12,217 Views
Registered: ‎07-01-2015

Re: VHDL external/hierarchical names support for simulations

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Hi marco@ms,

 

Please share a test case.

Thanks,
Arpan
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Participant marco@ms
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12,207 Views
Registered: ‎02-24-2016

Re: VHDL external/hierarchical names support for simulations

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Hi Arpan,

 

Please find attached it the full test bench.

 

The error I got is already from Analysis:

 

  • [HDL 9-806] Syntax error near "<". ["C:/Projects/X6/400M/logic/rbp/04_sim/rbp_chirp_dec_tb.vhd":272]

You can see directly in line 272 that the line is just

alias uut_do_dav is <<signal uut.do_dav_mux0 : std_logic>>;

 

I tried to change the scope of the declaration,  but i get the same error.

External signals are introduced in VHDL 2008, could it be this the reason?

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Moderator
Moderator
12,205 Views
Registered: ‎07-01-2015

Re: VHDL external/hierarchical names support for simulations

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Hi marco@ms,

 

Did you enable VHDL 2008?

With VHDL2008 I am not seeing any syntax error.

Thanks,
Arpan
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Participant marco@ms
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12,199 Views
Registered: ‎02-24-2016

Re: VHDL external/hierarchical names support for simulations

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yeah that must be the issue!

 

But I can't find the VHDL 2008 Type!

 

I can only choose VHDL ( Verilog, System Verilog, VHDL ) but not VHDL 2008

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Moderator
Moderator
12,197 Views
Registered: ‎07-01-2015

Re: VHDL external/hierarchical names support for simulations

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Hi marco@ms,

 

Which Vivado version are you using?

Thanks,
Arpan
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Participant marco@ms
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12,191 Views
Registered: ‎02-24-2016

Re: VHDL external/hierarchical names support for simulations

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I am using Vivado 2015.4

 

I just found that i have to use: set_property enable_vhdl_2008 1

 

However, I then get this error:

 

ERROR: [XSIM 43-4187] File "C:/Projects/X6/400M/logic/rbp/04_sim/rbp_chirp_dec_tb.vhd" Line 272 : The "Vhdl 2008 External Name" is not supported yet for simulation.

 

Is that so?

If yes, how can i then monitor and access signals in modules down in the hierarchy?

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Participant marco@ms
Participant
20,611 Views
Registered: ‎02-24-2016

Re: VHDL external/hierarchical names support for simulations

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For those who are interested the answer (for Vivado 2015.4) is NO, as you can read from the error message below:

 

ERROR: [XSIM 43-4187] File "C:/Projects/X6/400M/logic/rbp/04_sim/rbp_chirp_dec_tb.vhd" Line 272 : The "Vhdl 2008 External Name" is not supported yet for simulation.

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Visitor gordongeo
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7,673 Views
Registered: ‎06-20-2017

Re: VHDL external/hierarchical names support for simulations

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Hi,

 

I have absolutely the same problem. 

 

Although it does recognize VHDL 2008 external signals feature (after my definition of vhd file as VHDL2008), but  Vivado can't find my test signals in design hierarchy.  

 

For example for next expression:

 

val <= <<signal top_sim.top_design.v_sig : std_logic>>; 

 

I get  -  [VRFC 10-92] v_sig is not declared in top_design["top_sim.vhd":164]

 

If I put v_sig on top simulation level top_sim.vhd it does find this signal and proceed with simulation, but all idea for external signal usage is to find signals inside hierarchy or to put value to signal which is deeply inside hierarchy of the design !!!

 

If I choose the signal that on entity of second level (one below top_sim.vhd), I get:

 

[XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

 

Looks like this feature full of bugs in its first supported version of Vivado 2017.1 that I use !!!

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Xilinx Employee
Xilinx Employee
7,665 Views
Registered: ‎08-10-2015

Re: VHDL external/hierarchical names support for simulations

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Hi @gordongeo,

 

 

Please share the design files.

 

 

Thanks,

Sunilkumar

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Visitor gordongeo
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4,617 Views
Registered: ‎06-20-2017

Re: VHDL external/hierarchical names support for simulations

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Hi suniku,

 

I send you just example 2 level very simple design to see the problem.

 

 

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Xilinx Employee
Xilinx Employee
4,605 Views
Registered: ‎08-10-2015

Re: VHDL external/hierarchical names support for simulations

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Hi @gordongeo,

 

There are syntax errors in your design files that you shared.

1. you are using entity name instead of instantiation name to access signals using external names.

2. Absolute path should start with "."

3. You are accessing the signal before its entity instantiation.

 

top_design_inst: top_design
   port map (
     rst  => iRst,
     clk  => iClk,
     din1 => iDin1,
     din2 => iDin2,
     dout => oDout
   );
 
val <= <<signal .top_sim.top_design_inst.v_sig : std_logic>>;

 

With the above changes in top_sim.vhd file design working fine with 2017.1.

  

Thanks,

Sunilkumar

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Visitor gordongeo
Visitor
4,594 Views
Registered: ‎06-20-2017

Re: VHDL external/hierarchical names support for simulations

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Thanks Sunilkumar,

 

You're right. Now it's work.

It make sense to put some notice in documents about what did you mentioned:

 

1. The block instantiation name (not an entity name) should be used to access signals while using external names.

2. Accessing to the signal should be after its entity instantiation.

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