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Visitor carrexev
Visitor
185 Views
Registered: ‎03-21-2019

VHDL not showing output

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Hii I have the following vhdl which should implement an adder/substracter for a 2 bit signed signal input and output a result every X time defined by the port integr_time.

My issue is that in simulation the block works just fine, but when i input digital signals to the the arty through the chipset ports i dont get any output.

I tested vaious cases and with other vhdl and this is the only one that doesn't work for me.

Any tips?

 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity AdderSubstr1bit is
Port ( clk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (1 downto 0);
enable : in std_logic;
res : out STD_LOGIC_VECTOR (31 downto 0);
integr_time: in std_logic_vector(31 downto 0));
end AdderSubstr1bit;

architecture Behavioral of AdderSubstr1bit is
signal cnt : std_logic_vector(31 downto 0) := (others=>'0');
signal aux_res : signed (31 downto 0) := (others=>'0');
begin
process(clk)
begin

if (enable = '1') then
if (rising_edge(clk)) then
cnt <= std_logic_vector(unsigned(cnt) + 1);
if (data = "11") then
aux_res <= aux_res - 1;
elsif (data = "01") then
aux_res <= aux_res + 1;
end if;
end if;
else
 cnt <= (others=>'0');
 aux_res <= (others=>'0');
end if;
if (cnt = integr_time) then
res <= std_logic_vector(aux_res);
cnt <= (others=>'0');
aux_res <= (others=>'0');

end process;
end Behavioral;

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1 Solution

Accepted Solutions
Observer ryandunn19
Observer
129 Views
Registered: ‎06-05-2018

Re: VHDL not showing output

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Try something like this:

process(clk)
variable temp_res : signed(31 downto 0); begin if rising_edge(clk) then if enable = '1' then
if data = "11" then
temp_res := aux_res - 1;
elsif data = "01" then
temp_res := aux_res + 1;
else
temp_res := aux_res;
end if; if cnt = std_logic_vector(unsigned(integr_time) - 1) then
cnt <= (others => '0');
res <= std_logic_vector(temp_res);
aux_res <= (others => '0');
else cnt <= std_logic_vector(unsigned(cnt) + 1); aux_res <= temp_res;
end if; else cnt <= (others=>'0'); aux_res <= (others=>'0'); end if; end if; end process;

Now all of the signals are synchronous to the clock. Also, it is not recommended to use asynchronous resets (ug901 pg. 69). I don't think you need a reset for this, since the signals are initialized to zero and they are reset to zero when enable is 0. In fact, the enable is kind of acting as an active-low reset (reset if enable = 0, otherwise operate normally). 

7 Replies
Scholar dpaul24
Scholar
174 Views
Registered: ‎08-07-2014

Re: VHDL not showing output

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@carrexev,

You need to change your coding style and learn more about VHDL.

Assuming all your signals are synchronous, you should be checking their status at the rising edge of the clock. You are checking for the enable = '1' at the highest level.

Another tip -  you have no reset signal. It is good to have one, you may connect it to the development board reset pin. When the reset is asserted, all internal signals must be reset. An asynchronous reset should serve the purpose here. Something like...

        if reset = '1' then 
        -- reset all internal signals
        elsif rising_edge(clk) then
        .
        -- all other validations here
        .
        end if;

 

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Scholar drjohnsmith
Scholar
171 Views
Registered: ‎07-09-2009

Re: VHDL not showing output

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That code has a few problems,

look at the warnings and erros produced by the tools, start by looking at the sensetivity list warnings.

 

 

 

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Visitor carrexev
Visitor
162 Views
Registered: ‎03-21-2019

Re: VHDL not showing output

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Sorry if it is a bit obvious but I am editing on Vivado and it doesn't show any warnings. What tool you recommend?

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Visitor carrexev
Visitor
151 Views
Registered: ‎03-21-2019

Re: VHDL not showing output

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my data signal is asynchronus, i didnt mention it sry.
I will include the reset port since it looks like a good way to reset the block.
However do you see which error could lead to not having any output? I am not used to usee vhdl but on ther blocks i don't have this problem.
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Adventurer
Adventurer
142 Views
Registered: ‎10-31-2017

Re: VHDL not showing output

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I did a cursory look at your code and the first thing that stood out is the lack of enable at your sensitivity list. It should be

process(clk, enable)

if you want/need to code the way you did.

As @drjohnsmith wrote, you should look closely at the synthesis warnings as it should have a warning related to incomplete sensitivity list. Behavioral simulation does work but if you run post synthesis simulation, it will show a different result.

 

I also agree with @dpaul24 , there are better ways of coding, using as much synchronous logic as possible. You should take a look at the coding templates the tool (Vivado?) has with examples for several constructs, adders amongst them.

 

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Observer ryandunn19
Observer
130 Views
Registered: ‎06-05-2018

Re: VHDL not showing output

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Try something like this:

process(clk)
variable temp_res : signed(31 downto 0); begin if rising_edge(clk) then if enable = '1' then
if data = "11" then
temp_res := aux_res - 1;
elsif data = "01" then
temp_res := aux_res + 1;
else
temp_res := aux_res;
end if; if cnt = std_logic_vector(unsigned(integr_time) - 1) then
cnt <= (others => '0');
res <= std_logic_vector(temp_res);
aux_res <= (others => '0');
else cnt <= std_logic_vector(unsigned(cnt) + 1); aux_res <= temp_res;
end if; else cnt <= (others=>'0'); aux_res <= (others=>'0'); end if; end if; end process;

Now all of the signals are synchronous to the clock. Also, it is not recommended to use asynchronous resets (ug901 pg. 69). I don't think you need a reset for this, since the signals are initialized to zero and they are reset to zero when enable is 0. In fact, the enable is kind of acting as an active-low reset (reset if enable = 0, otherwise operate normally). 

Visitor carrexev
Visitor
90 Views
Registered: ‎03-21-2019

Re: VHDL not showing output

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thank you all for the tips. I used a similar code that the one you proposed and it worked. 

Maybe what i am wrong but what i get that was making and issue is the fact that i was using as and auxiliar variable as a signal declared outside the process. when i introduced a variable temp the synthesis simulation started showing some correct results

 

Sorry for bothering you all and thank you very mach

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