cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
26,518 Views
Registered: ‎10-16-2013

VHDL package not comiled in work library -> Vivado 2013.3 Simulator

Hi,

 

have the following package with some record declarations:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 

package interface_pack is
    
    type data_set_32bit is record
        data :std_logic_vector(31 downto 0);
        valid :std_logic;
        eol :std_logic;
        eof :std_logic;
        toggle: std_logic;
    end record;
    
    type data_set_16bit is record
        data :std_logic_vector(15 downto 0);
        valid :std_logic;
        eol :std_logic;
        eof :std_logic;
        toggle: std_logic;
    end record;
    
    type data_set_12bit is record
        data :std_logic_vector(11 downto 0);
        valid :std_logic;
        eol :std_logic;
        eof :std_logic;
        toggle: std_logic;
    end record;
    
    type data_set_32bit_complex is record
        data :std_logic_vector(63 downto 0);
        valid :std_logic;
        eol :std_logic;
        eof :std_logic;
        toggle: std_logic;
    end record;
    
end interface_pack;

 


In my Design file i use the package with "use work.interface_pack.all;" but when i will simulate it i get the following error:

 

ERROR:  [VRFC 10-149] 'interface_pack' is not compiled in library work...

 


I don't understand this, because in the Vivado Sources view (Libraries Tab) the package exists in work -> see screenshot.

 

Has anyone an idea?

 

Thank's

lib.jpg
0 Kudos
11 Replies
Highlighted
Xilinx Employee
Xilinx Employee
26,492 Views
Registered: ‎10-24-2013

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

Hi,
Try change the design to not use the package, meaning remove the "use" reference to the utils package and add component declarations.
Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
26,471 Views
Registered: ‎07-16-2008

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

Please check the .prj file located in <project>.sim/sim_1directory. It looks the package file is not included in the compile list.

 

If this is the case, try setting the package file as global include file.

Select the package files and check "IS_GLOBAL_INCLUDE" in the Properties tab in the Source File Properties window.

If it still doesn't work, you'll have to create a custom .prj with the complete file list and launch simulation from command line (the xelab command can be referenced from .log file located in sim_1 directory).

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Adventurer
Adventurer
26,332 Views
Registered: ‎12-20-2010

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

I had the same problem.  I can confirm that checking "IS_GLOBAL_INCLUDE" fixed the issue in Vivado 2013.2.

Thanks!

0 Kudos
Highlighted
Moderator
Moderator
26,304 Views
Registered: ‎04-17-2011

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

@voco-mannheim Is the issue fixed at your end? Do you have any further questions on this thread?

Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Explorer
Explorer
26,238 Views
Registered: ‎11-27-2008

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

I have a similar problem, in general, with VHDL files that are instantiated like this:

u_xyz : entity work.abc

...

instead of:

component abc

...

end component

...

u_xyz : abc

...

 

If I run simulation I get the message: "[VRFC 10-149] 'abc' is not compiled in library work". However, I if I use the 2nd method, at least once, then switch back to the 1st method, it works. So I think the problem is that Vivado is not (re)compiling the modules into library work, unless the module is specifically declared as a component, in the same file where it is used. The first example is perfectly valid VHDL and should be supported.

 

Is there a way to 'force' Vivado to just recompile a module, into its library (work)? I haven't found one. I think this has caused problems in other situations as well.

 

Thanks,

Dan

 

0 Kudos
Highlighted
22,992 Views
Registered: ‎09-23-2012

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

@debrajr, This is still a problem in 2014.4. Any idea if it is on the list to be fixed in 2015.1?
0 Kudos
Highlighted
22,972 Views
Registered: ‎09-23-2012

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

The global include is not as bad a workaround as I initially thought. you only need to make it global for a single run, than you can unclick the global and it will continue to work.
0 Kudos
Highlighted
Adventurer
Adventurer
13,599 Views
Registered: ‎08-17-2009

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

Ist there any news on this matter? It seems still to be an issue with 2016.2.

 

I cannot compile VHDL sources which compiled fine in ISE: I need to add work.MyEntity before every entity I'm using and specify the "global include" for all the files, then it compiles.

It is a possible workaround, but it is a lot of work and I need to alter all the sources (to add the "work." prefixes).

 

Has anyone found a better way?

 

Thanks,

Stefan

 

0 Kudos
Highlighted
11,493 Views
Registered: ‎04-21-2017

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

instead of
use package_name.all
try this:
use work.package_name.all
0 Kudos
Highlighted
Contributor
Contributor
4,357 Views
Registered: ‎08-02-2016

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

I have the same problem while I am trying to simulation a child module in project.

and solved it by enabling IS_GLOBAL_INCLUDE in Source File Properties.

0 Kudos
Highlighted
Explorer
Explorer
4,233 Views
Registered: ‎09-29-2016

Re: VHDL package not comiled in work library -> Vivado 2013.3 Simulator

Solved for me by just making the compile order correct - i.e. put packages first in the compile order