02-04-2014 01:43 AM
have the following package with some record declarations:
package interface_pack is
type data_set_32bit is record
data :std_logic_vector(31 downto 0);
type data_set_16bit is record
data :std_logic_vector(15 downto 0);
type data_set_12bit is record
data :std_logic_vector(11 downto 0);
type data_set_32bit_complex is record
data :std_logic_vector(63 downto 0);
In my Design file i use the package with "use work.interface_pack.all;" but when i will simulate it i get the following error:
ERROR: [VRFC 10-149] 'interface_pack' is not compiled in library work...
I don't understand this, because in the Vivado Sources view (Libraries Tab) the package exists in work -> see screenshot.
Has anyone an idea?
02-05-2014 02:43 AM
02-08-2014 08:11 PM
Please check the .prj file located in <project>.sim/sim_1directory. It looks the package file is not included in the compile list.
If this is the case, try setting the package file as global include file.
Select the package files and check "IS_GLOBAL_INCLUDE" in the Properties tab in the Source File Properties window.
If it still doesn't work, you'll have to create a custom .prj with the complete file list and launch simulation from command line (the xelab command can be referenced from .log file located in sim_1 directory).
03-17-2014 02:48 PM
I had the same problem. I can confirm that checking "IS_GLOBAL_INCLUDE" fixed the issue in Vivado 2013.2.
03-22-2014 10:37 AM
@voco-mannheim Is the issue fixed at your end? Do you have any further questions on this thread?
03-31-2014 07:13 PM - edited 03-31-2014 07:16 PM
I have a similar problem, in general, with VHDL files that are instantiated like this:
u_xyz : entity work.abc
u_xyz : abc
If I run simulation I get the message: "[VRFC 10-149] 'abc' is not compiled in library work". However, I if I use the 2nd method, at least once, then switch back to the 1st method, it works. So I think the problem is that Vivado is not (re)compiling the modules into library work, unless the module is specifically declared as a component, in the same file where it is used. The first example is perfectly valid VHDL and should be supported.
Is there a way to 'force' Vivado to just recompile a module, into its library (work)? I haven't found one. I think this has caused problems in other situations as well.
01-04-2015 07:23 PM
01-06-2015 09:10 AM
11-25-2016 09:25 AM
Ist there any news on this matter? It seems still to be an issue with 2016.2.
I cannot compile VHDL sources which compiled fine in ISE: I need to add work.MyEntity before every entity I'm using and specify the "global include" for all the files, then it compiles.
It is a possible workaround, but it is a lot of work and I need to alter all the sources (to add the "work." prefixes).
Has anyone found a better way?
06-12-2017 10:24 PM
I have the same problem while I am trying to simulation a child module in project.
and solved it by enabling IS_GLOBAL_INCLUDE in Source File Properties.
07-13-2017 12:25 AM
Solved for me by just making the compile order correct - i.e. put packages first in the compile order