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YannZ80
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Registered: ‎09-26-2020

VHDL post-implementation timing simulation results

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Hi,

I have successfully implemented a design inside a Spartan S7 FPGA. It works fine on the target hardware (xc7s25csga225-1).

It also works fine for all kinds of functional simulations. However, when trying to perform post implementation timing simulation the design does not work fine anymore.

By looking at the "Vivado Design Suite User Guide" document I have read:

IMPORTANT: Post-Synthesis and Post-Implementation timing simulations are supported for Verilog
only. There is no support for VHDL timing simulation. If you are a VHDL user, you can run post synthesis
and post implementation functional simulation (in which case no SDF annotation is required and the
simulation netlist uses the UNISIM library). You can create the netlist using the write_vhdl Tcl
command. For usage information, refer to the Vivado Design Suite Tcl Command Reference Guide
(UG835) [Ref 7].

Does it mean that attempting to run post-timing simulation with VHDL would lead to wrong / inconsistent results ?

Thanks for your help,

Yann

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drjohnsmith
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@richardhead 

 

I've been around even longer, 45 years, since the XC2000 parts. 

  I also have never run post P&R simulation in anger, just to try it out and see a few times just in case I do need it in anger one time.

I totally agree with you on timing constraints and functional simulation,

 

   

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YannZ80
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Also, I have set "Mixed" inside the simulation box options:

YannZ80_0-1614509509357.png

Thanks,

Yann

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drjohnsmith
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Two things,

IMHO , and by experience, Xilinx support is terrible, the evidence is they are just not interested, 

   Im guess its because they are west coast of US based

 

Second,

   Post implementation, your code is no longer VHDL , 

 

What does matter is the top level of the test bench,

    I think the simulator only supports the limited std_logic and std_logic_vector ,

       so if your test bench needs to use these as its IO.

 

       

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richardhead
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Registered: ‎08-01-2012

Any particular reason you want to do a netlist simulation? It is usually much easier and much more effective to write a good RTL testbench and follow up by testing it on the real hardware.

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YannZ80
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In fact, @richardhead I think it was the process to be followed:

1. Perform RTL simulation

2. Once it's ok, perform synthetisis / implementation 

3. Perform timing simulation.

As it works fine on the target, may be step 3 is useless ???

Anyway, I will try to compare the results between post-implementation functional simulation (OK) and post-implementation timing simulation (not OK).
May be if it's a matter of wrong timing simulation model used.
I will let you know what I have found (if I find anything significant...) after comparing both kinds of simulation !

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richardhead
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nearly 20 years in the industry, I still have never run a post synth or implementation simulation, nor have I seen someone run one. With a good RTL testbench and correct timing specs, its just simpler to run the design on the board. Synthesis tools are very good nowadays - they are able to convert a lot of HDL to real circuits.

If the function simulation works, but the timing simulation is broken, I suggest that either you have timing problems or you have some specs not written for the design. Have you checked the timing reports? (not this asumes your design is fully synchronous)

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Registered: ‎01-22-2015

@YannZ80 

You can run post-timing simulation for your VHDL project as described by moderator, graces, in the following thread.

https://forums.xilinx.com/t5/Simulation-and-Verification/Simulation-behavioral-structural-functional-timing/m-p/879000#M23216 

However, as other have said, once you get past behavioral simulation and your project passes timing analysis then you may find it easiest/fastest to do further testing by running the design on the board.

Cheers,
Mark

drjohnsmith
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@richardhead 

 

I've been around even longer, 45 years, since the XC2000 parts. 

  I also have never run post P&R simulation in anger, just to try it out and see a few times just in case I do need it in anger one time.

I totally agree with you on timing constraints and functional simulation,

 

   

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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YannZ80
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Thanks to all of you for your help and experience sharing !

Yann

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