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Observer a.turowski
Observer
10,182 Views
Registered: ‎10-26-2012

VHDL rising_edge() not working properly with records

Hi all,

 

I am using ISim 13.4 (nt64). In one of my designs I have to pass quite a lot of clocks through the whole design hierarchy. As a convenience method I decided to create a VHDL record with all the clocks and pass the record rather than single signals between entities. Everything compiles without problems, but the simulation code where I use rising_edge() detects clock's edges only for the first clock in the record. Here is an excerpt from VHDL example showing the problem:

 

type CLOCKS_TYPE is record
clk_1 : std_logic;
clk_2 : std_logic;
end record;

 

signal clocks : CLOCKS_TYPE;

 

CLK_DRIVE_PROC: process

begin
  clocks.clk_1 <= '0';

  clocks.clk_2 <= '0';

  wait for 10ns;

  clocks.clk_1 <= '1';

  clocks.clk_2 <= '1';

  wait for 10ns;

end process;

 

CLK_1_PROC: process(clocks.clk_1)

begin

  if rising_edge(clocks.clk_1) then

    clk_1_cnt <= clk_1_cnt + 1;

  end if;

end process;

 

CLK_2_PROC: process(clocks.clk_2)

begin

  if rising_edge(clocks.clk_2) then

    clk_2_cnt <= clk_2_cnt + 1;

  end if;

end process;

 

In the code above only clk_1_cnt counter gets incremented in simulation - the one which driving clock is defined first in VHDL record. If I swap clocks order definitions around in VHDL record, only clk_2_cnt gets incremented. The same behavior is observed regardless of the number of clocks defined in VHDL record.

 

I've also checked that if one uses old school method of detecting clock edge:

 

if (clk'event and clk = '1') then .....

 

end if;

 

then all counters work fine in simulation. So it looks like it is something to do with rising_edge() function working correctly with VHDL records. Any thoughts why is that?

 

Best regards,

Adam

 

 

 

 

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10 Replies
Historian
Historian
10,177 Views
Registered: ‎02-25-2008

Re: VHDL rising_edge() not working properly with records

I just tested this with Aldec's Active-HDL 8.3 and it works fine.

 

It's a bug in ISim. Perhaps it was fixed in ISE 14?

----------------------------Yes, I do this for a living.
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Instructor
Instructor
10,173 Views
Registered: ‎08-14-2007

Re: VHDL rising_edge() not working properly with records

Works for me in ISE 14.7 ISIM.  Also in ISE 13.4 ISIM.

 

I'm running WinXP 32-bit, full ISIM license.

-- Gabor
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Instructor
Instructor
10,166 Views
Registered: ‎08-14-2007

Re: VHDL rising_edge() not working properly with records

Looking through the forums, I see a lot of issues with 64-bit ISIM.  If you have the option, I'd suggest trying to run the 32-bit version of ISIM to see if that fixes your problem.

-- Gabor
0 Kudos
5,434 Views
Registered: ‎04-13-2016

Re: VHDL rising_edge() not working properly with records

This is still a problem in Vivado 2015.3. We have resorted to using:

 

 if clk'event and clk = '1' then

 

in all our code because we understand the limitations of the statement rather than the unknown assocaited with spending time tracking down bugs in the simulator.

 

Regards, Thomas D.

 

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Explorer
Explorer
4,897 Views
Registered: ‎01-09-2012

Re: VHDL rising_edge() not working properly with records

I plunged into the same problem today. The problem is still present in 2015.4.2 I just tried a GTX component with the rxusrclk and txusrclk in a record and the txusrclk was ignored in rising_edge. Like the other authors the only fix was replacing the function rising_edge(clk) by (clk'event and clk = '1').

Tonight I will try ISIM 64bit in Vidado  2016.1 and report back what happens here.

 

Cheers

Goran

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Explorer
Explorer
4,892 Views
Registered: ‎09-13-2011

Re: VHDL rising_edge() not working properly with records

Works fine for me in ISE 14.7 and Vivado 2016.1.

 

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Explorer
Explorer
4,866 Views
Registered: ‎01-09-2012

Re: VHDL rising_edge() not working properly with records

Well it is still not working properly although at least the fist stated observation appears to be solved. However there is still some issue with the rising_edge function. Here my observation:

 

This code here does what it should:

txusrclk_ok_code.JPG

and in simulation it does:

txusrclk_ok_sim.JPG

Then lets just replace the line "if (txusrclk'event and (txusrclk = '1')) then" by "if rising_edge(txusrclk) then".

The code looks like the follows:

txusrclk_nok_code.JPG

But the simulation shows:

txusrclk_nok_sim.JPG

 

By the way: I defined txusrclk to be:

txusrclk : in    std_logic;

 

The only explanation I have is that txusrclk is not toggling between '0' and '1' but by something else? But I have no clue that Xilinx is doing in their GTX code or whether the ISIM has an issue or ISIM is presenting the values somehow different than handled internaly.

However, I agree with some pragmatic comments before: If I have a working solution, I am fine.

 

Cheers

Goran

 

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Xilinx Employee
Xilinx Employee
4,202 Views
Registered: ‎09-13-2014

Re: VHDL rising_edge() not working properly with records

Hi,

 

We had some known issue regarding clocking event on record element, which have been fixed but the current issue that you have mentioned is not reproducible with simple test case that I wrote.

 

Will it be possible for you to share test case?

 

--dhiRAj

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Xilinx Employee
Xilinx Employee
4,169 Views
Registered: ‎10-24-2013

Re: VHDL rising_edge() not working properly with records

Hi @a.turowski

 

Can you please share the project archive with which we can reproduce the issue at our end for further debug?

Thanks,Vijay
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Observer ikalogic
Observer
866 Views
Registered: ‎08-23-2011

Re: VHDL rising_edge() not working properly with records

Same problem with ISE 14.7.

 

I am using a Spartan 6.

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