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Registered: ‎11-09-2019

VHDL test bench not working for Inout port

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Hi,

I have two VHDL file. IOtest and IOtest_tb(test bench file). I am trying to test one scenario which consitsts of inout port. But the simulation is not as expected. Please go through the attached vhdl files.

The signal p3_s is not getting 1 at 0ns rather it's getting updated at 5ns.

when signal ro_s='0' and sel_line_s='1' p3 should read the value from ip. But this is also not happening. Kindly check and help me on this. I am stuck in this from a week.

 

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: VHDL test bench not working for Inout port

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1. p3_s is driven from the TB and the DUT. While it is driven to '1' from the TB, it is driven to 'U' from the DUT, and 'U' always wins.

2. You have three if..else statements inside the process inside the DUT. The final else "wins" and assigns p3 to 'Z', meaning the value of '1' comes from the TB

 

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: VHDL test bench not working for Inout port

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1. p3_s is driven from the TB and the DUT. While it is driven to '1' from the TB, it is driven to 'U' from the DUT, and 'U' always wins.

2. You have three if..else statements inside the process inside the DUT. The final else "wins" and assigns p3 to 'Z', meaning the value of '1' comes from the TB

 

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Registered: ‎11-09-2019

Re: VHDL test bench not working for Inout port

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Thanks you. Your answer helped me to understand the inout concept.
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