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Teacher
Teacher
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Registered: ‎07-09-2009

VHDL variables in simulation

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What is the current status of the Xilinx simulators to show VHDL variables in the trace window ?

Im on a tablet right now, so cant try, but I seem to rember we needed to use other simulators like Modelsim to be able to view vhdl variables,

I had look in forums, but we have all sorts of 'answers' , yes / no / may be.  

any one have a thought please ?

 

 

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Registered: ‎01-22-2015

Re: VHDL variables in simulation

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In Vivado v2018.3 during Functional Simulation, when I do the following:

1) Select "Check All Filters" in the Scope window settings

2) Select "Variable" in the in the Objects window settings

then the Objects window shows VHDL variables and their values - from both the testbench and the design-under-test.  However, the "Add to Wave Window" option for the VHDL variable is greyed-out.   

So, I think answer is no.

check_all_filters.jpgsim_variable.jpg

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Highlighted
706 Views
Registered: ‎01-22-2015

Re: VHDL variables in simulation

Jump to solution

In Vivado v2018.3 during Functional Simulation, when I do the following:

1) Select "Check All Filters" in the Scope window settings

2) Select "Variable" in the in the Objects window settings

then the Objects window shows VHDL variables and their values - from both the testbench and the design-under-test.  However, the "Add to Wave Window" option for the VHDL variable is greyed-out.   

So, I think answer is no.

check_all_filters.jpgsim_variable.jpg

View solution in original post