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Adventurer
Adventurer
7,169 Views
Registered: ‎03-03-2014

VIVADO batch simulation problems

Hello,

 

I'm using VIVADO 2014.4, 64 bits, VHDL

 

I'm trying to use simulation in batch mode with makefiles.

It is new for me, but I have to as it is requested by the final user !!

 

 

1)  How to configure my testbench file from makefile ?

 

I want to configure my testbench file using VHDL generic.

 

I have the following VHDL :

 

entity tb_test is
  generic
    (
    -- System Configuration
    constant N_CONFIG                  : integer := 2    );
end entity tb_test;

architecture sim of tb_test is

 

I tried the following command

 

xelab -initfile ../xxx/xsim.ini -debug typical tb_test -s xsim_tb_test -generic_top "N_CONFIG= 2"

but I get :

Running: C:/Xilinx/Vivado/2014.4/bin/unwrapped/win64.o/xelab.exe -initfile ../xxx/xsim.ini -debug typical tb_test -s xsim_tb_test -generic_top N_CONFIG= 2

Multi-threading is on. Using 2 slave threads.

Starting static elaboration

ERROR: [VRFC 10-1509] unknown actual generic literal value 2 for generic n_config ignored

 

I also tried

xelab -initfile ../xxx/xsim.ini -debug typical tb_test -s xsim_tb_test -generic_top "N_CONFIG=2"

But I get

 

Running: C:/Xilinx/Vivado/2014.4/bin/unwrapped/win64.o/xelab.exe -initfile ../xxx/xsim.ini -debug typical tb_test -s xsim_tb_test -generic_top N_CONFIG 2

Multi-threading is on. Using 2 slave threads.

ERROR: [XSIM 43-3225] Cannot find design unit work.2 in library work located at xsim.dir/work.

 

 

I just can understand what is wrong !

I'm wondering if it usable with VHDL ?

 

Any one has a clue ?

 

2) How to initialize Microblaze memory file with elf ?

In the GUI mode, I assign .elf files for implementation and simulation and it works fine.

Here in batch mode, I just dont see where and how to do it !

 

Any one has a clue ?

 

Thank you !

 

Stephane.

 

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