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forgodbok
Visitor
Visitor
1,904 Views
Registered: ‎10-05-2016

VIVADO "Open IP Example Design" template

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Hello,

 

I wanted to simulate some IP core.

 

Since I'm used to using verilog, I created project with verilog option

 

Then I generated IP core which I want. I clicked "Open IP example design" by righ-click of IP core.

 

VIVADO generated example simulation....but it was VHDL.

 

Is there any initial setting for verilog template?

 

Thank you!

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prathikm
Moderator
Moderator
1,891 Views
Registered: ‎09-15-2016

Hi @forgodbok,

 

You can refer the respective IP Product Guide to see if Verilog example design is provided for the core or not. This will be usually in the core specs table section. As an example below.

 

01.PNG

 

Go to this link (link1) then search the IP name > Click on IP name > Documentation > Select the guide to refer.

 

Thanks

Prathik

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2 Replies
prathikm
Moderator
Moderator
1,892 Views
Registered: ‎09-15-2016

Hi @forgodbok,

 

You can refer the respective IP Product Guide to see if Verilog example design is provided for the core or not. This will be usually in the core specs table section. As an example below.

 

01.PNG

 

Go to this link (link1) then search the IP name > Click on IP name > Documentation > Select the guide to refer.

 

Thanks

Prathik

-----------------------------------------------------------------------------------

Don't forget to reply, kudo, and mark the appropriate post as 'accept as solution'.

-----------------------------------------------------------------------------------

View solution in original post

forgodbok
Visitor
Visitor
1,878 Views
Registered: ‎10-05-2016

Thank you 

 

you are correct...it was specified in product guide.

 

 

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