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Visitor julien-niu
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Registered: ‎07-08-2019

[VRFC 10-3140] automatic variable 'trans' cannot be written in this context

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I tried to write systemVerilog simulation code. However, when I tried to write some value to class "trans", it show this error. Does anyone know how to solve this issue?

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Contributor
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Registered: ‎10-25-2018

Re: [VRFC 10-3140] automatic variable 'trans' cannot be written in this context

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Ah, it's the non-blocking assignments '<=' that are the problem. The simplest thing would be to change those to blocking assignments "=". However, this illustrates a possible issue with the SystemVerilog LRM regarding the restriction: "Automatic variables and elements of dynamically sized array variables shall not be written with nonblocking, continuous, or procedural continuous assignments." and how that applies to class properties, since simulators seem inconsistent on this point. I'll look into it some more.

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Visitor julien-niu
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Registered: ‎07-08-2019

Re: [VRFC 10-3140] automatic variable 'trans' cannot be written in this context

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It seems automatic variable cannot be wrttien with some values. After I change 'trans' from automatic to global (static?) variable, it works. Anybody know why??

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Contributor
Contributor
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Registered: ‎10-25-2018

Re: [VRFC 10-3140] automatic variable 'trans' cannot be written in this context

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Show us your code and all will (hopefully) be revealed.

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Visitor julien-niu
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Registered: ‎07-08-2019

Re: [VRFC 10-3140] automatic variable 'trans' cannot be written in this context

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task main;
        forever begin
            transaction trans;
            gen2driv.get( trans );
            @( posedge vif.clk );
            vif.valid <= 1;
            vif.a <= trans.a;
            vif.b <= trans.b;

            @( posedge vif.clk );
            vif.valid <= 0;
            trans.c <= vif.c;

            @( posedge vif.clk );
            trans.display( "[ DRIVER ]" );
            no_transactions++;
        end
endtask
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Contributor
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Registered: ‎10-25-2018

Re: [VRFC 10-3140] automatic variable 'trans' cannot be written in this context

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Did you change the declaration of a, b, and c to static in order to get the code working?

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Visitor julien-niu
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Registered: ‎07-08-2019

Re: [VRFC 10-3140] automatic variable 'trans' cannot be written in this context

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No. I try to put 'transaction trans' out of main function, then it works. So, does it become static variable if I put 'trans' out of main function?

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Contributor
Contributor
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Registered: ‎10-25-2018

Re: [VRFC 10-3140] automatic variable 'trans' cannot be written in this context

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Ah, it's the non-blocking assignments '<=' that are the problem. The simplest thing would be to change those to blocking assignments "=". However, this illustrates a possible issue with the SystemVerilog LRM regarding the restriction: "Automatic variables and elements of dynamically sized array variables shall not be written with nonblocking, continuous, or procedural continuous assignments." and how that applies to class properties, since simulators seem inconsistent on this point. I'll look into it some more.

View solution in original post

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