06-19-2019 07:17 AM
I get this error when runnign xsim on vivado 2018.3. I can't see the actual recursion in my instance u_output_axi_comm_quad. Is the error saying u_output_axi_comm_quad has an instance of itself ?
ERROR: [VRFC 10-3427] illegal recursive design instantiation, instance name 'u_output_axi_comm_quad' [/wrk/2018.3/continuous/2018_12_06_2405991/data/secureip/gthe2_channel/gthe2_channel_002.vp:31464]
ERROR: [VRFC 10-3427] illegal recursive design instantiation, instance name 'u_output_axi_comm_quad' [/wrk/2018.3/continuous/2018_12_06_2405991/data/secureip/gthe2_common/gthe2_common_002.vp:123184]
ERROR: [VRFC 10-3427] illegal recursive design instantiation, instance name 'u_output_axi_comm_quad' [/wrk/2018.3/continuous/2018_12_06_2405991/data/secureip/gthe2_channel/gthe2_channel_002.vp:53932]
ERROR: [VRFC 10-3427] illegal recursive design instantiation, instance name 'u_output_axi_comm_quad' [/wrk/2018.3/continuous/2018_12_06_2405991/data/secureip/gthe2_channel/gthe2_channel_002.vp:54806]
06-19-2019 07:29 AM
Hi @joebrt ,
Either rename the parent module, or the instanced module.
Consider the following RTL:
1: module top();
3: top inst_of_top;
There is an instance of module top within the definition of module top. This can be fixed by changing the module name "top" in either lines 1 or 3.
06-19-2019 08:31 AM
My design structure is like this:
---INST_B (this instance contains the module that causes the actual recursion error)
TOP_A is basically a wrapper for B. I can simulate INST_B (without error) if I set it as top. But once I try and simulate TOP_A I get the illegal recursion. I've renamed TOP_A and INST_B.
To me it seems that I should have the error when I simulate INST_B.
06-19-2019 06:50 PM
Can you attach the top wrapper for a look?
06-20-2019 05:58 AM
06-20-2019 11:24 PM
INFO: [VRFC 10-3369] going to verilog side to elaborate module 'aurora_64b66b_1duplex_exdes' [Z:/SVN/CUST_SOW17/src_XC7VX980T_2FFG1930C/cat2015/output_axi_comm_quad.vhd:85]
INFO: [VRFC 10-3232] compiling module 'aurora_64b66b_1duplex_exdes(USE_CORE_TRAFFIC=1,USR_CLK_PCOUNT=9'b011111111,USE_LABTOOLS=0)' [Z:/SVN/CUST_SOW17/src_XC7VX980T_2FFG1930C/cat2015/aurora_64b66b_duplex_1_ex/imports/aurora_64b66b_1duplex_exdes.v:71]
ERROR: [VRFC 10-3427] illegal recursive design instantiation, instance name 'u_output_axi_comm_quad' [/wrk/2018.3/continuous/2018_12_06_2405991/data/secureip/gthe2_channel/gthe2_channel_002.vp:28751]
it looks the error occurs when compiling the submodule aurora_64b66b_1duplex_exdes within u_output_axi_comm_quad. You may want to inspect the line in bold.
06-24-2019 06:09 AM
06-25-2019 01:25 AM
I don't think the parent model is called in the secureip model that the error points to. But the error message does look confusing.
It's not clear from the current provided files what could be wrong.
Is it possible to archive the project and send for further investigation?
06-25-2019 05:27 PM
I've sent you a private message regarding the file transfer. Please check it.
06-28-2019 12:52 AM
I can reproduce the failure using Vivado Simulator, but not Questasim. It looks to be a tool issue with Vivado Simulator, as the compile order looks to be identical between the two simulators.
Is it possible for you to upgrade to 2019.1 and try out simulation? Migrating from the 2018.3 project introduces some compile errors regarding IP library.
06-28-2019 05:57 AM
Thanks. The tool version is dictated by customer. I may have to live with this for the moment.