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Visitor yinbinjun
Visitor
344 Views
Registered: ‎12-10-2018

[VRFC 10-597] element index -1 into num_write_words_dc is out of bounds

Simulation warning 

[VRFC 10-597] element index -1 into num_write_words_dc is out of bounds ["G:/wrk/2017.4/nightly/2017_12_15_2086221/packages/customer/vivado/data/ip/xilinx/fifo_generator_v13_2/simulation/fifo_generator_vlog_beh.v":8130]

This warning occurs when I instantiate the FIFO

FIFO interface

捕获.PNG

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3 Replies
Moderator
Moderator
297 Views
Registered: ‎09-15-2016

Re: [VRFC 10-597] element index -1 into num_write_words_dc is out of bounds

Hi @yinbinjun ,

Can you please share a test case to check this issue at our end.

Thanks & Regards,
Sravanthi B
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Visitor yinbinjun
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264 Views
Registered: ‎12-10-2018

Re: [VRFC 10-597] element index -1 into num_write_words_dc is out of bounds

 

 thank you for your reply,this is my design sources and its Tb sources
///////////////////// design sources 
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2018/12/28 10:56:28
// Design Name: 
// Module Name: FIFO_Test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module FIFO_Test(
		//input 
		clk,
		rst_n,
		//output
		dout,
		full,
		empty,
		prog_full,
		
		rd_en,
		wr_en,
		din_w,
		cnt_w
);
//input
input 			clk;
input 			rst_n;
//output
output          full;
output          empty;
output          prog_full;
output          rd_en;
output          wr_en;

output [63:0]    din_w;
output [15:0]    dout;
output [8:0]     cnt_w;
//wire
wire         	full;
wire         	wr_en;
wire        	empty;
wire         	rd_en;
wire         	clk;
wire         	srst;
wire         	prog_full;

wire [63:0]   	din_w;
wire [15:0]    	dout;
wire [8:0]    	cnt_w;

//reg
reg[8:0] 		cnt;

//assin
assign wr_en = (full== 1'd0 && cnt >= 9'd2 && cnt <= 9'd48)?1:0;
assign rd_en = (cnt >= 9'd32 && cnt <= 9'd128)?1:0; 

assign srst  = rst_n;
assign cnt_w = cnt;
        
//logic
reg[15:0] Data_buf_1;
reg[15:0] Data_buf_2;
reg[15:0] Data_buf_3;
reg[15:0] Data_buf_4;

reg[15:0] Data_buf_N_1;
reg[15:0] Data_buf_N_2;
reg[15:0] Data_buf_N_3;
reg[15:0] Data_buf_N_4;
	
always @ (posedge clk or negedge rst_n)
begin 
	if (!rst_n)begin
		Data_buf_1     <= 16'd4;
		Data_buf_2     <= 16'd3;
		Data_buf_3     <= 16'd2;
		Data_buf_4 	   <= 16'd1;
		
	end else begin 
		Data_buf_1 	   <= Data_buf_N_1;
		Data_buf_2     <= Data_buf_N_2;
		Data_buf_3     <= Data_buf_N_3;
		Data_buf_4     <= Data_buf_N_4;
	end
end

always @ (*)
begin 
	if( wr_en )begin
		Data_buf_N_1 = Data_buf_1 + 16'd4;
		Data_buf_N_2 = Data_buf_2 + 16'd4;
		Data_buf_N_3 = Data_buf_3 + 16'd4;
		Data_buf_N_4 = Data_buf_4 + 16'd4;
	end else begin
		Data_buf_N_1 = Data_buf_1;
		Data_buf_N_2 = Data_buf_2;
		Data_buf_N_3 = Data_buf_3;
		Data_buf_N_4 = Data_buf_4;			
	end 
end

always@(posedge clk or posedge rst_n)
	if(rst_n) 
		cnt<=9'd0;
	else begin
	if(cnt==9'd128) 
		cnt<=cnt;
	else 
		cnt<=cnt+9'd1;
end


assign din_w ={Data_buf_1,Data_buf_2,Data_buf_3,Data_buf_4};

 fifo_generator_0 FIFO(
	.full(full),
	.din(din_w),
	.wr_en(wr_en),
	.empty(empty),
	.dout(dout),
	.rd_en(rd_en),
	.clk(clk),
	.srst(srst),
	.prog_full(prog_full)
	);
endmodule

///////////////////// TB sources 
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2018/12/28 11:03:39
// Design Name: 
// Module Name: FIFO_Top_TB
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module FIFO_Top_TB(
    );
    // Inputs
    reg clk_i;
    reg rst_i;
    
   wire          full;
   wire          empty;
   wire          prog_full;
   wire          rd_en;
   wire          wr_en;
	
   wire [63:0]   din_w;
   wire [15:0]   dout;
   wire [8:0]    cnt_w;
   initial 
       begin
	// Initialize Inputs4
	clk_i = 0;
	rst_i = 0;
        // Wait 100 ns for global reset to finish
	#5;rst_i=1;
	#15;rst_i=0;
	#3000 ;
	end
	always
	begin
		#5 clk_i=~clk_i;
	end
FIFO_Test FIFO_Test( //input .clk(clk_i), .rst_n(rst_i), //output .full(full), .empty(empty), .prog_full(prog_full), .dout(dout), .rd_en(rd_en), .wr_en(wr_en), .din_w(din_w), .cnt_w(cnt_w) ); endmodule

 

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Visitor yinbinjun
Visitor
261 Views
Registered: ‎12-10-2018

Re: [VRFC 10-597] element index -1 into num_write_words_dc is out of bounds

update FIFO configure picture捕获121212.PNG

Thank you for your help,Looking forward to your reply

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