UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
426 Views
Registered: ‎06-25-2018

VRFC 10-900

Jump to solution

Hello,

I have a very small design that fails simulation.

The design consists of 1 AXI VIP configured as an AXI-Lite master and 1 GPIO configured as 1-bit output only.

All that the test-bench does is output a 0 in the GPIO,  then a 1, then a 0.

I get the following error message:

VRFC 10-900 "Incompatible complex type assignment" at this line in the test-bench:

mst_agent = new("master vip agent", DUT.axi_vip_0.inst.IF);
 
I found one post in the Xilinx forum that talks about this.  The solution was to change the simulation language to Verilog.  I made sure that I have Verilog selected but I still get the same error.

Do  you have any suggestions what I am doing wrong?

Thanks,

Jacques

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
401 Views
Registered: ‎07-16-2008

回复: VRFC 10-900

Jump to solution

What is the Vivado version that you're running?

Are you able to run simulation for the AXI VIP example design?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
402 Views
Registered: ‎07-16-2008

回复: VRFC 10-900

Jump to solution

What is the Vivado version that you're running?

Are you able to run simulation for the AXI VIP example design?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Adventurer
Adventurer
395 Views
Registered: ‎06-25-2018

回复: VRFC 10-900

Jump to solution

I didn't try this one.  But I am able to run simulation in the v_tpg_o_ex example design which also contains a AXI VIP.

When I run the post_synthesis functional simulation I get a different message:

VRFC 10-93: IF is not declared under prefix inst

In the sources hierarchy of the example design I see:

ex_sim_axi_vip_0_0

  inst : axi_vip_v1_1_3_top

    ? IF : xil_defaultlib.axi_vip_if 

In my design I don't have the IF under inst.

So this could be the problem.  How can I fix this?

Regards,

Jacques

0 Kudos
Adventurer
Adventurer
391 Views
Registered: ‎06-25-2018

回复: VRFC 10-900

Jump to solution

I found the problem.

In the AXI_VIP customization window, Advanced Settings, field HAS RRESP must be 0.

Now the simulation runs.  But I still don't have IF under inst in the sources hierarchy.

Regards,

Jacques

 

 

0 Kudos
Adventurer
Adventurer
365 Views
Registered: ‎06-25-2018

回复: VRFC 10-900

Jump to solution

Hi,

Setting the HAS RRESP parameter to 1 makes the simulation runs in behavioral mode but not in post-systhesis mode.  I am still getting the VRFC 10-93 error message.

So I need a way to add the IF interface in the axi_vip hierarchy under inst.

Could you please provide a way to do this?

Thanks,

Jacques

0 Kudos
Adventurer
Adventurer
359 Views
Registered: ‎06-25-2018

回复: VRFC 10-900

Jump to solution

I meant setting the HAS RRESP parameter to 0 in my previous post.

Sorry about that.

0 Kudos