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Contributor
Contributor
2,014 Views
Registered: ‎10-16-2017

VTScalar: Cannot add child node to scalar type

I am trying to run behavioral simulation of my design however I get an error after starting simulation data flow analysis. The output of TCL console informs:

Starting simulation data flow analysis
terminate called after throwing an instance of 'std::logic_error'
what(): VTScalar: Cannot add child node to scalar type
ERROR: [XSIM 43-3312] Signal SIGABRT received.
Printing stacktrace.
...

I have no idea how to debug such issues, can I ask for some advice?

I use Vivado 2017.3.

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8 Replies
Moderator
Moderator
1,937 Views
Registered: ‎11-09-2015

Re: VTScalar: Cannot add child node to scalar type

Hi @mkru,

 

Could you give more information on your design? What are you trying to simulate?

Do you have a test case?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
1,895 Views
Registered: ‎10-16-2017

Re: VTScalar: Cannot add child node to scalar type

@florentw

Thanks for reply.

I have everything that is needed to reproduce the issue: https://github.com/m-kru/sync_scrambler .

Use commit faa10b4 and try to run behavioral simulation of test bench in Vivado. I have successfully simulated this design in ghdl.

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Moderator
Moderator
1,870 Views
Registered: ‎09-15-2016

Re: VTScalar: Cannot add child node to scalar type

Hi @mkru,

 

Thanks for sharing the link to get the design files.

Can you please let me know which OS are you using? I tried running the behavioural simulation at my end on a windows 7 64bit machine. It ran successfully as shown in below screenshot. Please let me know if i am missing any step to reproduce this issue.

 

behav_sim.JPG

 

Thanks & Regards,
Sravanthi B

 

 

Thanks & Regards,
Sravanthi B
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Contributor
Contributor
1,864 Views
Registered: ‎10-16-2017

Re: VTScalar: Cannot add child node to scalar type

@bandi

RELEASE=18.1
CODENAME=serena
EDITION="Cinnamon 64-bit"
DESCRIPTION="Linux Mint 18.1 Serena"
DESKTOP=Gnome

uname -a

Linux 4.8.0-56-generic #61~16.04.1-Ubuntu SMP Wed Jun 14 11:58:22 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux

If you do not use the most recent commit then you are not missing any step to reproduce the issue.

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Moderator
Moderator
1,844 Views
Registered: ‎04-24-2013

Re: VTScalar: Cannot add child node to scalar type

Hi @mkru

 

Mint Linux is not currently a supported Operating System, check User Guide 973 for the list.

 

Supported.PNG

 

Can you try in one of the above versions of Linux?

 

Best Regards
Aidan

 

 

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Contributor
Contributor
1,823 Views
Registered: ‎10-16-2017

Re: VTScalar: Cannot add child node to scalar type

@amaccre Sorry I do not have time for such experiment.

 

My Linux Mint is based on Ubuntu 16.04.1 LTS (64-bit) and there is a support for Ubuntu 16.04.2 LTS (64-bit).

I doubt there is any significant difference between 16.04.1 and 16.04.2. 

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Newbie thornschuh
Newbie
1,516 Views
Registered: ‎09-14-2017

Re: VTScalar: Cannot add child node to scalar type

Hi, 

I have the same problem with Vivado 2018.1 running on Ununtu 16.04 LTS.

I was able to track it down to a specific language construct. The following test code will reproduce the error.

It runs fine when you replace the subtype declaration of type t_data with the second variant (commented out below).

I observed the same behavior already with 2017.4, but no problems in 2017.2

 

 

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity tb_test is
  Port (
    S_AXI_WDATA : IN  std_logic_vector(31 downto 0)
  
   );
end tb_test;

architecture Behavioral of tb_test is

 -- The following definition Crashes with Vivado 2018.1
 -- but works with 2017.2 on the same machine
 subtype t_data is std_logic_vector(S_AXI_WDATA'range);
 
 -- This works
 --subtype t_data is std_logic_vector(S_AXI_WDATA'high downto S_AXI_WDATA'low);

begin

process
variable t : t_data;
begin
  t := (others=> '0');
  
  report "Finsihed";
  wait;

end process;


end Behavioral;

Error log is this:

Running: /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab -wto 4b1980be59de4ef38c584dad3163bbce --incr --debug typical --relax --mt 8 -L work -L secureip --snapshot tb_test_behav work.tb_test -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
terminate called after throwing an instance of 'std::logic_error'
  what():  VTScalar: Cannot add child node to scalar type
ERROR: [XSIM 43-3312] Signal SIGABRT received.
Printing stacktrace...

[0] /home/thomas/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/Ubuntu/libstdc++.so.6(__gnu_cxx::__verbose_terminate_handler()+0x15d) [0x7f0b63c7333d]
[1] /home/thomas/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/Ubuntu/libstdc++.so.6(+0x8e316) [0x7f0b63c71316]
[2] /home/thomas/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/Ubuntu/libstdc++.so.6(+0x8e361) [0x7f0b63c71361]
[3] /home/thomas/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/Ubuntu/libstdc++.so.6(+0x8e578) [0x7f0b63c71578]
[4] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x6d35b8]
[5] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x6d335b]
[6] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x6d000d]
[7] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x6caed1]
[8] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x6a3c0a]
[9] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x6ad5e4]
[10] /home/thomas/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/libxsimverific.so(Verific::VhdlVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f0b6506f666]
[11] /home/thomas/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/libxsimverific.so(Verific::VhdlVisitor::Visit(Verific::VhdlProcessStatement&)+0x69) [0x7f0b6506b0d9]
[12] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x6a5175]
[13] /home/thomas/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/libxsimverific.so(Verific::VhdlVisitor::TraverseArray(Verific::Array const*)+0x86) [0x7f0b6506f666]
[14] /home/thomas/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/libxsimverific.so(Verific::VhdlVisitor::Visit(Verific::VhdlArchitectureBody&)+0xa5) [0x7f0b6506d465]
[15] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x69fe87]
[16] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x6a1ee5]
[17] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x6a9860]
[18] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x66f635]
[19] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x46cd09]
[20] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x47d932]
[21] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x44fb9f]
[22] /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xf0) [0x7f0b6331a830]
[23] /home/thomas/opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab() [0x46a101]

Done
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Newbie thornschuh
Newbie
1,308 Views
Registered: ‎09-14-2017

Re: VTScalar: Cannot add child node to scalar type

Hi, any update on this?

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