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Adventurer
Adventurer
182 Views
Registered: ‎10-31-2017

Varying error behaviour on post synthesis simulation

Tool is Vivado 2018.3, device is Zynq.

 

I have a testbench that exercises part of the logic of the FPGA/PL. Behavioral simulation works fine every time.

 

Synthesis on the PL logic runs OK. However, when I try to run the post synthesis functional simulation, I have varying errors.  Below, the excerpts of two consecutive attempts:

 

INFO: [VRFC 10-163] Analyzing VHDL file "C:/svn/branches/Dev0.1/PL/resources/source/sequencer.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'sequencer'
WARNING: [VRFC 10-3607] overwriting existing primary unit 'sequencer' [C:/svn/branches/Dev0.1/PL/resources/source/sequencer.vhd:29]
INFO: [VRFC 10-163] Analyzing VHDL file "C:/svn/branches/Dev0.1/PL/resources/source/spi_adc.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'SPI_ADC'
WARNING: [VRFC 10-3607] overwriting existing primary unit 'spi_adc' [C:/svn/branches/Dev0.1/PL/resources/source/spi_adc.vhd:27]
INFO: [VRFC 10-3107] analyzing entity 'ad_capture'
WARNING: [VRFC 10-3607] overwriting existing primary unit 'ad_capture' [C:/svn/branches/Dev0.1/PL/resources/source/spi_adc.vhd:208]
INFO: [VRFC 10-3107] analyzing entity 'ad_transfer_clock_gen'
WARNING: [VRFC 10-3607] overwriting existing primary unit 'ad_transfer_clock_gen' [C:/svn/branches/Dev0.1/PL/resources/source/spi_adc.vhd:494]
run_program: Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 1590.113 ; gain = 399.535
INFO: [USF-XSim-69] 'compile' step finished in '10' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/svn/branches/Dev0.1/PL/SAR_IP/SAR_IP.sim/demod_full_tb/synth/func/xsim' Vivado Simulator 2018.3 Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2018.3/bin/unwrapped/win64.o/xelab.exe -wto f1da3dfacdfe460883e930ae6f8c1b18 --incr --debug typical --relax --mt 2 -generic_top USE_INTERLEAVE=1 -generic_top SIMULATION_PERIOD=12.5 ns -generic_top -generic_top DEMOD_CHANNELS=2 -generic_top AD_SINC_INITIAL_DELAY=5.5 -L xil_defaultlib -L secureip --snapshot demod_full_tb_func_synth xil_defaultlib.demod_full_tb -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-3146] binding entity 'demodulation' does not have generic 'max_demod_channels' [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:42] ERROR: [VRFC 10-3146] binding entity 'demodulation' does not have generic 'demod_channels' [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:43] ERROR: [VRFC 10-3146] binding entity 'demodulation' does not have generic 'demod_ram_start' [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:44] ERROR: [VRFC 10-3146] binding entity 'demodulation' does not have generic 'demod_ram_size' [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:45] ERROR: [VRFC 10-3146] binding entity 'demodulation' does not have generic 'enable_demod_test_tables' [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:47] ERROR: [VRFC 10-718] formal port <Clk> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:50] ERROR: [VRFC 10-718] formal port <Rst> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:51] ERROR: [VRFC 10-718] formal port <AdcData> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:52] ERROR: [VRFC 10-718] formal port <FrameSync> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:53] ERROR: [VRFC 10-718] formal port <AcqSync> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:54] ERROR: [VRFC 10-718] formal port <StabEnd> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:55] ERROR: [VRFC 10-718] formal port <AdDataReady> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:56] ERROR: [VRFC 10-718] formal port <DemodAcqEn> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:57] ERROR: [VRFC 10-718] formal port <BankSel> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:58] ERROR: [VRFC 10-718] formal port <Interleave> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:59] ERROR: [VRFC 10-718] formal port <Address> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:60] ERROR: [VRFC 10-718] formal port <Wen> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:61] ERROR: [VRFC 10-718] formal port <Ena> does not exist in entity <demodulation>. Please compare the definition of block <demodulation> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:62] INFO: [#UNDEF] Sorry, too many errors.. ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit demod_full_tb in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-99] Step results log file:'C:/svn/branches/Dev0.1/PL/SAR_IP/SAR_IP.sim/demod_full_tb/synth/func/xsim/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/svn/branches/Dev0.1/PL/SAR_IP/SAR_IP.sim/demod_full_tb/synth/func/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. launch_simulation: Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1590.113 ; gain = 880.809 ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

INFO: [VRFC 10-163] Analyzing VHDL file "C:/svn/branches/Dev0.1/PL/resources/source/dport_ram.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'dport_ram'
WARNING: [VRFC 10-3607] overwriting existing primary unit 'dport_ram' [C:/svn/branches/Dev0.1/PL/resources/source/dport_ram.vhd:27]
INFO: [VRFC 10-163] Analyzing VHDL file "C:/svn/branches/Dev0.1/PL/resources/source/demodulation.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'demodulation'
WARNING: [VRFC 10-3607] overwriting existing primary unit 'demodulation' [C:/svn/branches/Dev0.1/PL/resources/source/demodulation.vhd:29]
INFO: [VRFC 10-3107] analyzing entity 'demod_unit'
WARNING: [VRFC 10-3607] overwriting existing primary unit 'demod_unit' [C:/svn/branches/Dev0.1/PL/resources/source/demodulation.vhd:556]
INFO: [VRFC 10-3107] analyzing entity 'demod_macc'
WARNING: [VRFC 10-3607] overwriting existing primary unit 'demod_macc' [C:/svn/branches/Dev0.1/PL/resources/source/demodulation.vhd:673]
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:10 . Memory (MB): peak = 1785.840 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '10' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/svn/branches/Dev0.1/PL/SAR_IP/SAR_IP.sim/demod_full_tb/synth/func/xsim' Vivado Simulator 2018.3 Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2018.3/bin/unwrapped/win64.o/xelab.exe -wto f1da3dfacdfe460883e930ae6f8c1b18 --incr --debug typical --relax --mt 2 -generic_top USE_INTERLEAVE=1 -generic_top SIMULATION_PERIOD=12.5 ns -generic_top -generic_top DEMOD_CHANNELS=2 -generic_top AD_SINC_INITIAL_DELAY=5.5 -L xil_defaultlib -L secureip --snapshot demod_full_tb_func_synth xil_defaultlib.demod_full_tb -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-3146] binding entity 'sequencer' does not have generic 'wave_sync_count' [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:70] ERROR: [VRFC 10-3146] binding entity 'sequencer' does not have generic 'acq_sync_count' [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:71] ERROR: [VRFC 10-3146] binding entity 'sequencer' does not have generic 'stab_end_count' [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:72] ERROR: [VRFC 10-3146] binding entity 'sequencer' does not have generic 'xadc_conv_count' [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:73] ERROR: [VRFC 10-718] formal port <Clk> does not exist in entity <sequencer>. Please compare the definition of block <sequencer> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:76] ERROR: [VRFC 10-718] formal port <Rst> does not exist in entity <sequencer>. Please compare the definition of block <sequencer> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:77] ERROR: [VRFC 10-718] formal port <FrameSync> does not exist in entity <sequencer>. Please compare the definition of block <sequencer> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:79] ERROR: [VRFC 10-718] formal port <AcqSync> does not exist in entity <sequencer>. Please compare the definition of block <sequencer> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:80] ERROR: [VRFC 10-718] formal port <XadcSync> does not exist in entity <sequencer>. Please compare the definition of block <sequencer> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:81] ERROR: [VRFC 10-718] formal port <StabEnd> does not exist in entity <sequencer>. Please compare the definition of block <sequencer> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:82] ERROR: [VRFC 10-718] formal port <Frame_cfg> does not exist in entity <sequencer>. Please compare the definition of block <sequencer> to its component declaration and its instantion to detect the mismatch. [C:/svn/branches/Dev0.1/PL/resources/testbench/demod_full_tb.vhd:83] ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit demod_full_tb in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/svn/branches/Dev0.1/PL/SAR_IP/SAR_IP.sim/demod_full_tb/synth/func/xsim/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/svn/branches/Dev0.1/PL/SAR_IP/SAR_IP.sim/demod_full_tb/synth/func/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 1785.840 ; gain = 0.000 ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

I included a few lines before the elaboration step starts; notice the INFO and WARNINGS lines are different. Also notice these are two consecutive attempts with the same synthesized logic.

After a few attempts, simulation runs (no errors on the elaboration step) and simulation results are similar to behavioral's.

 

However this inconsistent behavior is weird.

 

Any ideas? Suggestions?

 

 

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3 Replies
Adventurer
Adventurer
147 Views
Registered: ‎10-31-2017

Re: Varying error behaviour on post synthesis simulation

I found a possible workaround: delete the directory contents of post synthesis simulation. Something like:

ProjName\ProjName.sim\TestBenchName\synth\func\xsim

 

I am not 100% sure yet because sometimes simulation runs even without the trick but it always run after deleting the directory contents and early today, when I was continously getting errors, I could simulate it right after deleting the directory.

 

Maybe that could provide some extra hint about the cause of the problem.

 

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Moderator
Moderator
123 Views
Registered: ‎05-31-2017

Re: Varying error behaviour on post synthesis simulation

Hi @eldercosta ,

At first, I suspect how deleting the XSIM directory had resolved the errors because the errors which you had specified are completely different and would not get resolved if you delete the XSIM directory as those need the modifications in testbench and UUT.

ERROR: [VRFC 10-3146] binding entity 'demodulation' does not have generic

 The above error occurs due to the generics(constant) are removed and usage of those generic are replaced with a constant value in post synthesis/post-Implementation Simulation. In earlier test bench, you had instance w.r.t to behavioral model(with generic involved) so the same test bench won't be applicable for post-synth/post-implementation simulation, you need to modify the test bench as generics get optimized during Synthesis.

ERROR: [VRFC 10-718] formal port <Clk> does not exist in entity

Regarding the above error, this might occur due to synthesis might have trimmed those signals. You can check the synthesis log file and see if the signals that are mentioned in the error have got trimmed.

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Adventurer
Adventurer
108 Views
Registered: ‎10-31-2017

Re: Varying error behaviour on post synthesis simulation

Hello, @shameera , thank you for chiming in.

At first, I suspect how deleting the XSIM directory had resolved the errors because the errors which you had specified are completely different and would not get resolved if you delete the XSIM directory as those need the modifications in testbench and UUT.

I expected the errors to be consistent, i.e. I get the very same error every time I try to run the simulation. However I get two different errors for two consecutive attempts. Also I would not expect the simulation to run at all.

The above error occurs due to the generics(constant) are removed and usage of those generic are replaced with a constant value in post synthesis/post-Implementation Simulation. In earlier test bench, you had instance w.r.t to behavioral model(with generic involved) so the same test bench won't be applicable for post-synth/post-implementation simulation, you need to modify the test bench as generics get optimized during Synthesis.

Again, if that were the case, the generics would be removed always and simulation would never run. However it runs and simulates.

funcsim.png

Regarding the above error, this might occur due to synthesis might have trimmed those signals. You can check the synthesis log file and see if the signals that are mentioned in the error have got trimmed.

Again, see above.

 

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