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Visitor
Visitor
8,324 Views
Registered: ‎03-13-2014

Verilog Compxlib Naming Issue

Hello,

 

Whenever I use compxlib to generate the simulation libraries for modelism I can't use the verilog verision (ex unisims_ver) to simulate because modelsim thinks the files don't exist. It believes this because the files all have @ symbols stuck in the path names (see attached). Is this normal behavior, and if not how can it be rectified?

 

Thanks.

library.png
4 Replies
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Xilinx Employee
Xilinx Employee
8,278 Views
Registered: ‎04-16-2012

Hello @jmayer16

Which version of ISE and modelsim are you using?

Thanks,
Vinay
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Xilinx Employee
Xilinx Employee
8,277 Views
Registered: ‎10-24-2013

Hi @jmayer16

 

What is the exact error you are seeing and what is your machine language settings?

 

Thanks,Vijay
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Visitor
Visitor
8,272 Views
Registered: ‎03-13-2014

Hi @vuppala,

 

I'm using Vivado 2014.2 and Modelsim-SE 10.1c.

 

Thanks.

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Moderator
Moderator
8,247 Views
Registered: ‎06-24-2015

Hi @jmayer16,

You are not using supported third-party simulator. Vivado 2014.2 can be used with QuestaSIM SE 10.2a. Please check the following link at page 10:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug973-vivado-release-notes-install-license.pdf

So, please try to use one of the supported simulators.

Thanks,
Nupur
Thanks,
Nupur
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