We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for
Did you mean:
Explorer
246 Views
Registered: ‎10-16-2018

## Verilog Literals

Hi @dgisselq ,

Could you pls, illustrate these two literals (Blue-Cirlced) :

What is 100_000_000 ?

Note : this picture from lsn_01

Thanks

Tags (1)
1 Solution

Accepted Solutions
Scholar
229 Views
Registered: ‎05-21-2015

## Re: Verilog Literals

Let's step through those.  First, ,both example literals begin with a 32'.  This means they each have 32-bits to them.  One literal is then followed by an `h` indicating a hexadecimal number, while the other is followed by a `d` indicating a decimal number.  Further, Verilog allows underscores within numbers as separators and the parser just ignores them.  Hence, the two numbers might also be written as 0xdeadbeef or 100000000 in a more traditional software context.  Notice how these are harder to read--the 100,000,000 value in particular, because there are so many zeros in it.  The underscores really helped to make it legible, although they didn't adjust its value at all.

Dan

4 Replies
Scholar
230 Views
Registered: ‎05-21-2015

## Re: Verilog Literals

Let's step through those.  First, ,both example literals begin with a 32'.  This means they each have 32-bits to them.  One literal is then followed by an `h` indicating a hexadecimal number, while the other is followed by a `d` indicating a decimal number.  Further, Verilog allows underscores within numbers as separators and the parser just ignores them.  Hence, the two numbers might also be written as 0xdeadbeef or 100000000 in a more traditional software context.  Notice how these are harder to read--the 100,000,000 value in particular, because there are so many zeros in it.  The underscores really helped to make it legible, although they didn't adjust its value at all.

Dan

Explorer
222 Views
Registered: ‎10-16-2018

## Re: Verilog Literals

could it stands for sth before define it?

Thanks

Scholar
214 Views
Registered: ‎05-21-2015

## Re: Verilog Literals

Did you notice that all of the characters in 32'hdead_beef where between a and f?  These are valid hexadecimal characters.  This is a fun number to use since it can also be "read", but it is still a number.  Mapping it to decimal, I get 3,735,928,559.

Note that this is a literal, not a variable.  It begins with a # (i.e. 32).  Variables cannot begin with numbers.  Therefore it doesn't need to be "defined", but rather is a value in its own right.

Dan

Explorer
210 Views
Registered: ‎10-16-2018