cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
367 Views
Registered: ‎01-26-2017

Verilog Parameters in Waveform Configuration

Hi,

       We're facing some issues with the waveform configuration of a project which uses Verilog files with parameters.

       We have .tcl scripts that create the project and set the parameters for the Verilog testbench using:

set_property generic [list \
    CHECK_PATTERN_FILE=[file normalize ${sim_dir}/tc_006/pattern/checker_file.pat] \
    ENABLE_IMU_INTERRUPTION=0 \
    SYSTEM_ID=$system_id\
    SYSTEM_MAJOR_REV_NB=[expr 0xAA]\
    SYSTEM_MINOR_REV_NB=[expr 0xBB]\
    SYSTEM_MICRO_REV_NB=[expr 0xCC]\
] [get_filesets sim_tc_006]

 

     When adding signals from that testbench into a waveform configuration file using XSim in Mixed-Mode simulation, the instance name that is used lists all the parameters of the verilog testbench:

add_wave {{/\tb_wrapper(CHECK_PATTERN_FILE="/work/develop/repo/prj/sim/tc_006/pattern/checker_file.pat",ENABLE_IMU_INTERRUPTION=0,SYSTEM_ID=26,SYSTEM_MAJOR_REV_NB=170,SYSTEM_MINOR_REV_NB=187,SYSTEM_MICRO_REV_NB=204) /system_tb_u/icn_master_bfm_gen/icn_master_bfm_u}}

 

And when saving the file, the fp_name property of the .wcfg then also contains the parameter list.

This is causing us some troubles, as every time the parameter list is modified or a parameter value changes, we lose all the waveform entries.

Do you have an idea how to get around this issue, to avoid having to edit the .wcfg file every time the testbench parameter list is changed?

 

Many thanks,

Vitor

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
205 Views
Registered: ‎05-01-2019

Hi,

Will it be possible for you to share the design?

Thanks,

Harika

Tags (1)
0 Kudos