UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie mbk
Newbie
204 Views
Registered: ‎03-09-2019

[Verilog and VHDL] inout does not get assigned to signal

Hello,

I am trying to get simple sram model to work.

The model file is in vhdl and i am used to working with verilog.

i've written the control logic and testbench in verilog and they seem to incorporate vhdl sram model well. However, the inout port (DQ)'s contents do not get passed on to a 'signal' (i think its a 'wire' in verilog terms?)

In attempting to write to sram, it writes 'XXXX_XXXX'.

Line 65 and 176 are important.

Architecture behave_arch Of async_128Kx8 Is
-- ...
begin
data_skew <= DQ after 1 ns; -- *** Line 65
-- ...

process -- main process
begin
-- ...
mem_array(conv_integer1(address_internal))(7 downto 0) := data_skew(7 downto 0); -- *** Line 176
-- ...
wait on write_enable, A, read_enable, DQ, data_skew;
end process;
end behave_arch;

Modifying line 176 to:

mem_array(conv_integer1(address_internal))(7 downto 0) := DQ(7 downto 0);

works well.

Thank you for looking into the issue.

0 Kudos