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Explorer
Explorer
1,404 Views
Registered: ‎05-07-2012

Verilog in Xilinx default library for a VHDL targeted simulation

Hello,

 

I've decided to use a third party simulator in lieu of the default Vivado simulator.  Our third party simulator license is VHDL only.  I soon discovered that there are quite a few Verilog files in the Xil_default library even though I set both the Vivado Target language and Simulator language settings to VHDL.  I'm not sure where the Verilog files came from but I'm guessing they were generated as part of the IP Catalog core creations.  So, Is there some way to get Vivado to actually adhere to the VHDL Simulator language and Target language settings?  Does Vivado throw VHDL into the mix when a user sets things to Verilog?

 

Thank you.

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Scholar jmcclusk
Scholar
1,389 Views
Registered: ‎02-24-2014

Re: Verilog in Xilinx default library for a VHDL targeted simulation

A lot of Xilinx IP from the IP catalog is Verilog only...    you really will need a mixed language license.

Don't forget to close a thread when possible by accepting a post as a solution.
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Moderator
Moderator
1,383 Views
Registered: ‎09-15-2016

Re: Verilog in Xilinx default library for a VHDL targeted simulation

Hi @sprl111,

 

Maybe you can try using structural simulation model by write_vhdl and using this netlist of core for simulation. (Reference link). report_compile_order -used_in simulation should return the vhdl netlist.

 

Regards,
Prathik
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Xilinx Employee
Xilinx Employee
1,368 Views
Registered: ‎07-16-2008

Re: Verilog in Xilinx default library for a VHDL targeted simulation

UG900, v2017.4, pg32, Table 2-6 illustrates the function of the simulator_language property.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug900-vivado-logic-simulation.pdf

 

As mentioned, quite a few Xilinx IPs deliver behavioral models in a single language.

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Explorer
Explorer
1,305 Views
Registered: ‎05-07-2012

Re: Verilog in Xilinx default library for a VHDL targeted simulation

I'm not understanding all of what you are saying here.

 

"Maybe you can try using structural simulation model by write_vhdl and using this netlist of core for simulation. "

I get this.  OK.  Sounds good.

 

 

"(Reference link). "

I looked at the link.  He's got to be kidding.  I have to do this for ever IP????!!!!  why even bother with a GUI?

 

report_compile_order -used_in simulation should return the vhdl netlist.

I have no idea what you are saying here.  This isn't even a sentence.

 

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Scholar richardhead
Scholar
1,297 Views
Registered: ‎08-01-2012

Re: Verilog in Xilinx default library for a VHDL targeted simulation

What IPs are you using? Memories can easily be inferred from HDL code, and with a memory a single clock FIFO can easily be built. For more complicated IPs, usually it's just easier to build a simulation model at the interface than have to drive all the other interfaces to get the IP up and running (and is much faster to simulate too - assuming your model is correct!)

 

There are ways to work around this to break free of the Vivado Simulator.

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