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Visitor
Visitor
303 Views
Registered: ‎06-02-2020

Vhdl 2008 is not supported yet for simulation once again...

This drives me crazy over and over again. While VHDL 2008 for synthesis seems to be pretty well supported in the last Vivado release, the lack of support for simulation is really, really annoying to say at least.

DO SOMETHING ABOUT IT NOW!!! PLEASE!!!

It seems like someone has tried at least, but gave up after the third attempt...

vhdl2008_isim.png

Regards
/F

 

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Explorer
Explorer
277 Views
Registered: ‎01-27-2008

Hi@Frippe 

See this link for support in a specific version. I always look at this guide per version to determine what my limitations are per language but tend to stick, these days, with SV. I can see per Appendix D of UG900 where VHDL2008 looks sparse.

https://forums.xilinx.com/t5/Simulation-and-Verification/XSIM-vs-Questa-Sim-gt-features/m-p/1153769/highlight/true#M30342

What, specifically, are you trying to do and can't?

Jerry

 

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Scholar
Scholar
265 Views
Registered: ‎08-01-2012

GHDL is a FOSS VHDL simulator - that has full 2008 support https://github.com/ghdl/ghdl

Otherwise activeHDL is cheap and even has some VHDL 2019 support.

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Visitor
Visitor
241 Views
Registered: ‎06-02-2020

I think ISIM is missing most of the VHDL 2008 features. I started this thread just out of frustration. Didn't really need any help. In any case, the last couple of missing features I had to maneuver around is unconstrained array, fixed_generic_pkg and to_string to mention a few.
I know that a lot of you have tried to get Xilinx attention on this topic without major success. This is sort of my attempt on getting their attention.
What worse is that Xilinx seems to be ditching VHDL altogether. And no, I don't want to change language.
GHDL, yes, why not. Only problem is that I will eventually deliver a number of Vivado designs to a customer and it needs to be simple, simple as in one tool and a free tool.
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Explorer
Explorer
203 Views
Registered: ‎01-27-2008

@Frippe 

I used to be a VHDL'er but SV won me over about 5 years ago. Now I write SV, but use VHDL as I need to... might be time to go over to the dark side?

 

 

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