09-23-2020 10:32 AM
This drives me crazy over and over again. While VHDL 2008 for synthesis seems to be pretty well supported in the last Vivado release, the lack of support for simulation is really, really annoying to say at least.
DO SOMETHING ABOUT IT NOW!!! PLEASE!!!
It seems like someone has tried at least, but gave up after the third attempt...
09-23-2020 02:31 PM
See this link for support in a specific version. I always look at this guide per version to determine what my limitations are per language but tend to stick, these days, with SV. I can see per Appendix D of UG900 where VHDL2008 looks sparse.
What, specifically, are you trying to do and can't?
09-23-2020 04:03 PM
09-23-2020 11:35 PM
09-24-2020 06:39 PM