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Newbie cstathis
Registered: ‎02-23-2015

Virtex-7 BRAM behavioral simulation read latency

I implemented a buffer with a Simple Dual-Port BRAM from logicores in Vivado 2014.3.1. First, addresses 0 through 7 are written to (8 bits wide, byte-write is enabled.) Then the data is read back with a width of 16 bits on addresses 0 through 3 in the same order. My write clock is 8 ns period and my read clock is 5 ns period.


Since I don't have output registers enabled, I expect the dout value to show up asynchronously some short period of time after the rising edge of the read clock. In behavioral simulation in Vivado, it appears to take an extra clock cycle for the value at the first read address to show up on the read port of the BRAM.


In the attached picture, the read port is enabled on the rising edge of the read clock at 865 ns. At that time, the read address is 0. The 16 bit value in memory at address 0 is 01f5. That value doesn't show up on dout until after the rising edge of the next read clock cycle at 870 ns... but after that, as the read address changes, the dout values show up right away.


Why does it take extra time to get the first word out of the BRAM? Is this a simulation quirk or do I just not understand how these BRAMs work?



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Xilinx Employee
Xilinx Employee
Registered: ‎07-16-2008

Re: Virtex-7 BRAM behavioral simulation read latency

The read enable is changed to '1' at the rising edge of read clock. It is sampled at the next rising edge.

Don't forget to reply, kudo, and accept as solution.
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